NDLI: Priority-driven, preemptive I/O controllers for real-time systems

Please wait, while we are loading the content...

Critical issues in mapping neural networks on message-passing multicomputers

Multinomial conjunctoid statistical learning machines

A bit-plane architecture for optical computing with two-dimensional symbolic substitution

The reconfigurable arithmetic processor

The performance potential of multiple functional unit processors

Exploiting parallel microprocessor microarchitectures with a compiler code generator

Analysis of memory referencing behavior for design of local memories

Performance evaluation of on-chip register and cache organizations

On the inclusion properties for multi-level cache hierarchies

A simulation study of two-level caches

Hyperswitch network for the hypercube computer

Analysis of bus hierarchies for multiprocessors

Extra group network: a cost-effective fault-tolerant multistage interconnection network

A partial-multiple-bus computer structure with improved cost effectiveness

Flagship: a parallel architecture for declarative programming

Toward a dataflow/von Neumann hybrid architecture

Resource requirements of dataflow programs

Priority-driven, preemptive I/O controllers for real-time systems

A kernel-independent, pipelined architecture for real-time 2-D convolution

Exploiting bit level concurrency in real-time geometric feature extractions

Measuring VAX 8800 performance with a histogram hardware monitor

Multiprocessor cache analysis using ATUM

Trade-offs between devices and paths in achieving disk interleaving

Design of a concurrent computer for solving systems of linear equations

The white dwarf: a high-performance application-specific processor

Solving partial differential equations in a data-driven multiprocessor environment

Scrambled storage for parallel memory systems

The architecture of a Linda coprocessor

Deadlock avoidance for systolic communication

Cache performance of vector processors

Distributed round-robin and first-come first-serve protocols and their applications to multiprocessor bus arbitration

An evaluation of directory schemes for cache coherence

Performance tradeoffs in cache design

A cache coherence scheme with fast selective invalidation

An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols

Destination tag routing techniques based on a state model for the LADM network

Regular CC-banyan networks

Traffic analysis of rectangular SW-banyan networks

High-performance multi-queue buffers for VLSI communications switches

A cache-based message passing scheme for a shared-bus multiprocessor

IMPULSE: a high performance processing unit for multiprocessors for scientific calculation

A characterization of sharing in parallel programs and its application to coherency protocol evaluation

A fetch-and-op implementation for parallel computers

Synchronizing processors through memory requests in a tightly coupled multiprocessor

Design and performance of special purpose hardware for time warp

The VMP multiprocessor: initial experience, refinements, and performance evaluation

The Wisconsin multicube: a new large-scale cache-coherent multiprocessor

Data buffer performance for sequential Prolog architectures

MASA: a multithreaded processor architecture for parallel symbolic computing

Parallel architecture for OPS5

Priority-driven, preemptive I/O controllers for real-time systems

Content Provider	ACM Digital Library
Author	Sprunt, B. Kirk, D. Sha, L.
Abstract	Current I/O controller architectures inhibit the use of priority-driven preemptive scheduling algorithms that can guarantee hard deadlines in real-time systems. This paper examines the effect of three I/O controller architectures upon schedulable utilization, which is the highest attainable resource utilization at or below which all deadlines can be guaranteed. FIFO request queueing, priority queueing, and priority queueing with preemptable service are simulated for a range of CPU computation to I/O traffic ratios. The results show that, for I/O bound tasks sets and zero preemption costs, priority queueing with preemptable service can provide a level of schedulable utilization 35% higher than that attainable with FIFO queueing and 20% higher than priority queueing and nonpreemptable service. Although the potential gain for priority queueing with preemptable service is large, further simulations that incorporate a time penalty for each preemption show that the gain is very sensitive to preemption cost. With preemption cost represented as a ratio of preemption time to the minimum task period, the level of schedulable utilization for priority queueing with preemptable service degrades to that of priority queueing with nonpreemptable service, for a preemption cost ratio of 0.04. A high level design of a preemptable I/O controller is described and the issues determining preemption cost are detailed along with techniques for its minimization.*.
Starting Page	152
Ending Page	159
Page Count	8
File Format	PDF
ISBN	0818608617
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1988-06-01
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Priority-driven, preemptive I/O controllers for real-time systems

Priority-driven, preemptive I/O controllers for real-time systems

A Stochastic Analysis Framework for Real-Time Systems under Preemptive Priority-Driven Scheduling

Mode Change Protocols for Priority-Driven Preemptive Scheduling (1988)

A Period Assignment Method for Fixed Priority Preemptive Real-time Systems

A preemptive priority-based disk I/O subsystem for the management of hard real-time disk traffic

Augmented priority ceiling protocol: task synchronization for preemptive real-time systems

Modeling Fixed Priority Non-Preemptive Scheduling with Real-Time Calculus

Preemptive and non-preemptive real-time uni-processor scheduling (1996).

Priority-driven, preemptive I/O controllers for real-time systems

Similar Documents

Priority-driven, preemptive I/O controllers for real-time systems

Priority-driven, preemptive I/O controllers for real-time systems

A Stochastic Analysis Framework for Real-Time Systems under Preemptive Priority-Driven Scheduling

Mode Change Protocols for Priority-Driven Preemptive Scheduling (1988)

A Period Assignment Method for Fixed Priority Preemptive Real-time Systems

A preemptive priority-based disk I/O subsystem for the management of hard real-time disk traffic

Augmented priority ceiling protocol: task synchronization for preemptive real-time systems

Modeling Fixed Priority Non-Preemptive Scheduling with Real-Time Calculus

Preemptive and non-preemptive real-time uni-processor scheduling (1996).

Priority-driven, preemptive I/O controllers for real-time systems