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  1. Proceedings of the 2005 workshop on MEmory performance (MEDEA '05)
  2. Data trace cache: an application specific cache architecture
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Memory performance: dealing with applications, systems and architecture
Dusty caches for reference counting garbage collection
Data trace cache: an application specific cache architecture
Making a case for split data caches for embedded applications
Exploiting the replication cache to improve cache read bandwidth cost effectively
An efficient synchronization technique for multiprocessor systems on-chip
Hiding message delivery and reducing memory access latency by providing direct-to-cache transfer during receive operations in a message passing environment
NPCryptBench: a cryptographic benchmark suite for network processors
Memory bandwidth optimization through stream descriptors
Energy-efficient instruction scheduling utilizing cache miss information
Analysis of embedded video coder systems: a system-level approach

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Data trace cache: an application specific cache architecture

Content Provider ACM Digital Library
Author Yalamanchili, Sudhakar Palem, Krishna V. Ramaswamy, Subramanian Sreeram, Jaswanth
Abstract Benefits of advances in processor technology have long been held hostage to the widening processor-memory gap. Off-chip memory access latency is one of the most critical parameters limiting system performance. Caches have been used as a way of alleviating this problem by reducing the average memory access latency. The memory bottleneck assumes greater significance for high performance computer architectures with high data throughput requirements such as network processors.This paper addresses the memory bottleneck with the goal of minimizing off-chip memory demand and average memory access latency by proposing the use of small application specific compiler-visible data trace caches. We focus on tree data structures which are responsible for a significant component of the memory traffic in several applications. We have observed that tree accesses create a simple to characterize trace of memory references and propose a data trace cache design to exploit the locality of reference in these data traces.Our study reveals that data trace caches can reduce the total number of misses from 7% to 53% for accesses to rooted tree data structures as compared to a conventional cache for a variety of applications for small cache sizes (256 - 1024 bytes). Such caches are in keeping with the philosophy of victim caches, stream buffers, and pre-fetch buffers in that relatively small investments in silicon can realize substantive reduction in off-chip memory bandwidth demand.
Starting Page 11
Ending Page 18
Page Count 8
File Format PDF
DOI 10.1145/1152779.1147354
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2005-09-17
Access Restriction Subscribed
Content Type Text
Resource Type Article
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