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  1. Proceedings of the 2005 workshop on MEmory performance (MEDEA '05)
  2. Memory performance: dealing with applications, systems and architecture
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Memory performance: dealing with applications, systems and architecture
Dusty caches for reference counting garbage collection
Data trace cache: an application specific cache architecture
Making a case for split data caches for embedded applications
Exploiting the replication cache to improve cache read bandwidth cost effectively
An efficient synchronization technique for multiprocessor systems on-chip
Hiding message delivery and reducing memory access latency by providing direct-to-cache transfer during receive operations in a message passing environment
NPCryptBench: a cryptographic benchmark suite for network processors
Memory bandwidth optimization through stream descriptors
Energy-efficient instruction scheduling utilizing cache miss information
Analysis of embedded video coder systems: a system-level approach

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Memory performance: dealing with applications, systems and architecture

Content Provider ACM Digital Library
Author Bartolini, S. Giorgi, R. Prete, C. A. Foglia, P.
Abstract In this issue of ACM SigArch Newsletter, we present ten papers from MEDEA-2005 Workshop held in conjunction with the IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT-2004) [1], [2].
Starting Page 1
Ending Page 2
Page Count 2
File Format PDF
DOI 10.1145/1152779.1147352
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2005-09-17
Access Restriction Subscribed
Content Type Text
Resource Type Article
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