NDLI: Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)

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Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)

Content Provider	ACM Digital Library
Author	David, Jean Pierre Daigneault, Marc-Andre
Abstract	Field-Programmable-Gate-Arrays are used increasingly to speed up applications in various fields of science. But as modern digital designs integrate hundreds of interconnected processing and memory units, the need for a higher level of abstraction to handle their descriptions is indisputable. This paper presents a beyond-RTL concurrent hardware description language that combines both Finite-State Machine (FSM) and constraint programming paradigms. At the featured level of abstraction, the user describes dynamic connections between data sources and sinks that may not always be ready to send or receive data tokens. The high-level description methodology enables a comprehensible description of behaviors such as data transfer synchronization, exclusivity, priority and constrained scheduling by the means of logical-implication rules constraining the data transfers authorizations. Dynamically connecting resources with potential combinatorial dependencies may lead to instability or deadlock. Such situations are automatically detected and fixed by the proposed compiler that generates a dedicated control-circuit optimizing the number of transfers that can be authorized at each clock cycle. The proposed design automation methodology is applied to the problem of deeply-pipelined vector reduction. A pipelined floating point accumulator and a matrix multiplication circuits are described with a few lines of code and automatically compiled into an FPGA. Results show that the synthesis results are comparable to those obtained with hand-written RTL but with much lower effort and time.
Starting Page	274
Ending Page	275
Page Count	2
ISBN	9781450318877
DOI	10.1145/2435264.2435337
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-02-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Hardware description language High-level synthesis Cyclic combinatorial relations Dataflow architectures Streaming interfaces
Content Type	Text
Resource Type	Article

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