NDLI: An FPGA memcached appliance

Please wait, while we are loading the content...

Building zynq® accelerators with Vivado® high level synthesis

Improving high level synthesis optimization opportunity through polyhedral transformations

Accelerating ncRNA homology search with FPGAs

Fully-functional FPGA prototype with fine-grain programmable body biasing

Word-length optimization beyond straight line code

Are FPGAs suffering from the innovator's dilemna?

Location, location, location: the role of spatial locality in asymptotic energy minimization

Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations

An FPGA based parallel architecture for music melody matching

FPGA bitstream compression and decompression using LZ and golomb coding (abstract only)

Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only)

Effect of fixed-point arithmetic on deep belief networks (abstract only)

Low power FPGA design using post-silicon device aging (abstract only)

Cross-platform FPGA accelerator development using CoRAM and CONNECT

Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers

Accelerating subsequence similarity search based on dynamic time warping distance with FPGA

GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction

Placement of repair circuits for in-field FPGA repair

Architectural enhancements in Stratix V™

Embedding-based placement of processing element networks on FPGAs for physical model simulation

A remote memory access infrastructure for global address space programming models in FPGAs

An FPGA memcached appliance

Indirect connection aware attraction for FPGA clustering (abstract only)

A novel multithread routing method for FPGAs (abstract only)

A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only)

Circuit optimizations to minimize energy in the global interconnect of a low-power--FPGA (abstract only)

Harnessing the power of FPGAs using altera's OpenCL compiler

Polyhedral-based data reuse optimization for configurable computing

Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform

Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering

Heracles: a tool for fast RTL-based design space exploration of multicore processors

Minimum energy operation for clustered island-style FPGAs

Area-efficient near-associative memories on FPGAs

C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction

High throughput and programmable online trafficclassifier on FPGA

Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)

FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only)

Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only)

Efficient system-level mapping from streaming applications to FPGAs (abstract only)

High-level synthesis with LegUp: a crash course for users and researchers

Faithful single-precision floating-point tangent for FPGAs

Sensing nanosecond-scale voltage attacks and natural transients in FPGAs

Improving bitstream compression by modifying FPGA architecture

Architecture support for custom instructions with memory operations

A latency-optimized hybrid network for clustering FPGAs (abstract only)

Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only)

FPGA-based HPC application design for non-experts (abstract only)

Defect recovery in nanodevice-based programmable interconnects (abstract only)

Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only)

A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)

AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on FPGA (abstract only)

A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only)

Hardware implemented real-time operating system (abstract only)

Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only)

Performance and toolchain of a combined GPU/FPGA desktop (abstract only)

Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only)

Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)

Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)

Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)

FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only)

An FPGA-based transient error simulator for evaluating resilient system designs (abstract only)

Automating resource optimisation in reconfigurable design (abstract only)

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only)

Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only)

Acceleration of the long read mapping on a PC-FPGA architecture (abstract only)

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)

Custom instruction generation and mapping for reconfigurable instruction set processors (abstract only)

High performance architecture for object detection in streamed video (abstract only)

An FPGA memcached appliance

Content Provider	ACM Digital Library
Author	AuYoung, Alvin Wright, Mitch Ranganathan, Parthasarathy Margala, Martin Lim, Kevin Chalamalasetti, Sai Rahul
Abstract	Providing low-latency access to large amounts of data is one of the foremost requirements for many web services. To address these needs, systems such as Memcached have been created which provide a distributed, all in-memory key-value store. These systems are critical and often deployed across hundreds or thousands of servers. However, these systems are not well matched for commodity servers, as they require significant CPU resources to achieve reasonable network bandwidth, yet the core Memcached functions do not benefit from the high performance of standard server CPUs. In this paper, we demonstrate the design of an FPGA-based Memcached appliance. We take Memcached, a complex software system, and implement its core functionality on an FPGA. By leveraging the FPGA's design and utilizing its customizable logic to create a specialized appliance we are able to tightly integrate networking, compute, and memory. This integration allows us to overcome many of the bottlenecks found in standard servers. Our design provides performance on-par with baseline servers, but consumes only 9% of the power of the baseline. Scaled out, we see benefits at the data center level, substantially improving the performance-per-dollar while improving energy efficiency by 3.2X to 10.9X.
Starting Page	245
Ending Page	254
Page Count	10
File Format	PDF
ISBN	9781450318877
DOI	10.1145/2435264.2435306
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-02-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Data centers Fpga Memcached appliance Energy efficiency Low power
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in