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Compilation and Pipeline Synthesis for Reconfigurable Architectures (1997)
| Content Provider | CiteSeerX |
|---|---|
| Author | Weinhardt, Markus |
| Description | . This paper gives a survey of a novel programming method for reconfigurable architectures. It combines techniques from vectorizing compilers, high-level synthesis, and hardware/software codesign: An imperative high-level language program specifies both the host program (software) and the coprocessor configuration (hardware) of the application. This renders reconfigurable architectures useful for users without hardware design experience. First, the input program is analyzed and vectorized. Then, for suitable loops, hardware pipelines are synthesized. They execute the loops' operators in parallel on the reconfigurable hardware, thus speeding up the program. Finally, a partitioner dynamically selects software or hardware execution for every loop. To show the feasibility of this method, we have built a prototypical "pipeline compiler". It automatically synthesizes coprocessors and integrates their configuration and control within the host program. Results of some experiments on a small FP... |
| File Format | |
| Language | English |
| Publisher | Verlag |
| Publisher Date | 1997-01-01 |
| Publisher Institution | In Reconfigurable Architecture Workshop |
| Access Restriction | Open |
| Subject Keyword | Novel Programming Method Host Program Hardware Design Experience Hardware Software Codesign Pipeline Synthesis Input Program Reconfigurable Hardware Small Fp Reconfigurable Architecture Coprocessor Configuration High-level Synthesis Imperative High-level Language Program Specifies Hardware Execution Hardware Pipeline Suitable Loop Prototypical Pipeline Compiler |
| Content Type | Text |
| Resource Type | Article |
