NDLI: Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise

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Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion

Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels

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Access Pattern Reshaping for eMMC-enabled SSDs

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Code Transformations Based on Speculative SDC Scheduling

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Global Routing with Inherent Static Timing Constraints

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Synthesis for Power-Aware Clock Spines

A Novel Way to Authenticate Untrusted Integrated Circuits

RRAM Based Lightweight User Authentication

EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICs

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Simulation-Guided Parameter Synthesis for Chance-Constrained Optimization of Control Systems

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SAT Solving using FPGA-based Heterogeneous Computing

Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm

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Toward Metrics of Design Automation Research Impact

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FEMTO: Fast Error Analysis in Multipliers through Topological Traversal

Pairwise Proximity-Based Features for Test Escape Screening

Defect Clustering-Aware Spare-TSV Allocation for 3D ICs

Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise

High Level Synthesis of RDF Queries for Graph Analytics

CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs

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Security Policy Enforcement in Modern SoC Designs

Protecting Endpoint Devices in IoT Supply Chain

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Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization

Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols

SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis

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Threshold Logic Synthesis Based on Cut Pruning

TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints

High Performance Global Placement and Legalization Accounting for Fence Regions

POLAR 3.0: An Ultrafast Global Placement Engine

Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization

A Flexible Architecture for Systematic Implementation of SoC Security Policies

ConFirm: Detecting Firmware Modifications in Embedded Systems using Hardware Performance Counters

Quantifying Timing-Based Information Flow in Cryptographic Hardware

Detecting Hardware Trojans in Unspecified Functionality Using Mutation Testing

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Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information

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Simulation of Noise in Neurons and Neuronal Circuits

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Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating Cost

A Contract Design Approach for Colocation Data Center Demand Response

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Statistical Learning in Chip (SLIC)

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications

Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories

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Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach

Transient Noise Bounds using Vectorless Power Grid Verification

1-Bit Compressed Sensing Based Framework for Built-in Resonance Frequency Prediction Using On-Chip Noise Sensors

Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines

A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis

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Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs

Hardware Accelerator Design for Data Centers

Modern Big Data Analytics for "Old-fashioned" Semiconductor Industry Applications

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Dynamically Resilient and Agile Fine-Grained Replication Configuration

Property-Directed Synthesis of Reactive Systems from Safety Specifications

Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States

On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation

Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection

ApproxEigen: An Approximate Computing Technique for Large-Scale Eigen-Decomposition

Modeling and Mitigation of Extra-SoC Thermal Coupling Effects and Heat Transfer Variations in Mobile Devices

Just Enough is More: Achieving Sustainable Performance in Mobile Devices under Thermal Limitations

Learning-Based Power Modeling of System-Level Black-Box IPs

Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes

GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints

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