NDLI: Variation-Aware Adaptive Tuning for Nanophotonic Interconnects

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Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion

Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels

A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems

Access Pattern Reshaping for eMMC-enabled SSDs

STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures

Self-Aware Cyber-Physical Systems-on-Chip

Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure

Self Learning Analog/Mixed-Signal/RF Systems: Dynamic Adaptation to Workload and Environmental Uncertainties

Formal Methods for Emerging Technologies

Code Transformations Based on Speculative SDC Scheduling

ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests

Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs

MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines

Global Routing with Inherent Static Timing Constraints

TILA: Timing-Driven Incremental Layer Assignment

Accelerate FPGA Routing with Parallel Recursive Partitioning

Synthesis for Power-Aware Clock Spines

A Novel Way to Authenticate Untrusted Integrated Circuits

RRAM Based Lightweight User Authentication

EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICs

BoardPUF: Physical Unclonable Functions for Printed Circuit Board Authentication

Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs

The (Low) Power of Less Wiring: Enabling Energy Efficiency in Many-Core Platforms Through Wireless NoC

Mathematical Models and Control Algorithms for Dynamic Optimization of Multicore Platforms: A Complex Dynamics Approach

Mitigating the Power Density and Temperature Problems in the Nano-Era

Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs

Analytically Modeling Power and Performance of a CNN System

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning

Robust Communication with IoT Devices using Wearable Brain Machine Interfaces

Simulation-Guided Parameter Synthesis for Chance-Constrained Optimization of Control Systems

A Mixed Discrete-Continuous Optimization Scheme for Cyber-Physical System Architecture Exploration

A User-Centric CPU-GPU Governing Framework for 3D Games on Mobile Devices

SAT Solving using FPGA-based Heterogeneous Computing

Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm

Evolving EDA Beyond its E-Roots: An Overview

DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives

Toward Metrics of Design Automation Research Impact

DA Vision 2015: From Here to Eternity

Impact of Loop Transformations on Software Reliability

Error-Tolerant Processors: Formal Specification and Verification

FEMTO: Fast Error Analysis in Multipliers through Topological Traversal

Pairwise Proximity-Based Features for Test Escape Screening

Defect Clustering-Aware Spare-TSV Allocation for 3D ICs

Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise

High Level Synthesis of RDF Queries for Graph Analytics

CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs

PUF-Based Authentication

Security Policy Enforcement in Modern SoC Designs

Protecting Endpoint Devices in IoT Supply Chain

A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration

Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling

Multi-Threaded Simics SystemC Virtual Platform

PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration

Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization

Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols

SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis

Learning Based Compact Thermal Modeling for Energy-Efficient Smart Building Management: (invited)

From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance

Security Analysis of Proactive Participation of Smart Buildings in Smart Grid

Buildings to Grid Integration: A Dynamic Contract Approach

On Relaxing Page Program Disturbance over 3D MLC Flash Memory

Variation-Aware Adaptive Tuning for Nanophotonic Interconnects

Threshold Logic Synthesis Based on Cut Pruning

TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems

Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints

High Performance Global Placement and Legalization Accounting for Fence Regions

POLAR 3.0: An Ultrafast Global Placement Engine

Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization

A Flexible Architecture for Systematic Implementation of SoC Security Policies

ConFirm: Detecting Firmware Modifications in Embedded Systems using Hardware Performance Counters

Quantifying Timing-Based Information Flow in Cryptographic Hardware

Detecting Hardware Trojans in Unspecified Functionality Using Mutation Testing

A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design

Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information

STAVES: Speedy Tensor-Aided Volterra-Based Electronic Simulator

Simulation of Noise in Neurons and Neuronal Circuits

Acceleration of Nested Conditionals on CGRAs via Trigger Scheme

Smartphone Analysis and Optimization based on User Activity Recognition

Perception-Aware Power Management for Mobile Games via Dynamic Resolution Scaling

A Unified Stochastic Model for Energy Management in Solar-Powered Embedded Systems

Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating Cost

A Contract Design Approach for Colocation Data Center Demand Response

Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs

Power-Down Circuit Synthesis for Analog/Mixed-Signal

Statistical Learning in Chip (SLIC)

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications

Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories

CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile Devices

A universal ordered NoC design platform for shared-memory MPSoC

Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach

Transient Noise Bounds using Vectorless Power Grid Verification

1-Bit Compressed Sensing Based Framework for Built-in Resonance Frequency Prediction Using On-Chip Noise Sensors

Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines

A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis

Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection

Optimization of FinFET-based circuits using a dual gate pitch technique

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs

Hardware Accelerator Design for Data Centers

Modern Big Data Analytics for "Old-fashioned" Semiconductor Industry Applications

Effective CAD Research in the Sea of Papers

Dynamically Resilient and Agile Fine-Grained Replication Configuration

Property-Directed Synthesis of Reactive Systems from Safety Specifications

Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States

On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation

Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection

ApproxEigen: An Approximate Computing Technique for Large-Scale Eigen-Decomposition

Modeling and Mitigation of Extra-SoC Thermal Coupling Effects and Heat Transfer Variations in Mobile Devices

Just Enough is More: Achieving Sustainable Performance in Mobile Devices under Thermal Limitations

Learning-Based Power Modeling of System-Level Black-Box IPs

Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes

GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints

A General and Exact Routing Methodology for Digital Microfluidic Biochips

TAU 2015 Contest on Incremental Timing Analysis: Incremental Timing and CPPR Analysis

iTimerC 2.0: Fast Incremental Timing and CPPR Analysis

OpenTimer: A High-Performance Timing Analysis Tool

iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal

Overview of the 2015 CAD Contest at ICCAD

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite

ICCAD-2015 CAD Contest in Incremental Timing-driven Placement and Benchmark Suite

Rebooting Computing and Low-Power Image Recognition Challenge

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