NDLI: The VTR project: architecture and CAD for FPGAs from verilog to routing

Please wait, while we are loading the content...

Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA

CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs

The VTR project: architecture and CAD for FPGAs from verilog to routing

Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones

A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction

Leveraging latency-insensitivity to ease multiple FPGA design

Multi-ported memories for FPGAs via XOR

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

Accelerating short read mapping on an FPGA (abstract only)

Adaptive FPGA-based robotics state machine architecture derived with genetic algorithms (abstract only)

Efficient in-system RTL verification and debugging using FPGAs (abstract only)

Post-silicon debugging targeting electrical errors with patchable controllers (abstract only)

Speedy FPGA-based packet classifiers with low on-chip memory requirements

A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications

Compiling high throughput network processors

Securing netlist-level FPGA design through exploiting process variation and degradation

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

A scalable approach for automated precision analysis

OCTAVO: an FPGA-centric processor family

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs

The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only)

A novel full coverage test method for CLBs in FPGA (abstract only)

Parallel FPGA placement based on individual LUT placement (abstract only)

Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only)

A real-time stereo vision system using a tree-structured dynamic programming on FPGA

A mixed precision Monte Carlo methodology for reconfigurable accelerator systems

Limit study of energy & delay benefits of component-specific routing

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing

FPGA-accelerated 3D reconstruction using compressive sensing

Optimizing SDRAM bandwidth for custom FPGA loop accelerators

Accelerator compiler for the VENICE vector processor

Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)

Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only)

Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only)

Early timing estimation for system-level design using FPGAs (abstract only)

Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation

Saturating the transceiver bandwidth: switch fabric design on FPGAs

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation

VirtualRC: a virtual FPGA platform for applications and tools portability

FCache: a system for cache coherent processing on FPGAs

A field programmable array core for image processing (abstract only)

Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only)

OpenCL memory infrastructure for FPGAs (abstract only)

Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)

X-ORCA: FPGA-based wireless localization in the sub-millimeter range

Impact of FPGA architecture on resource sharing in high-level synthesis

Reliability of a softcore processor in a commercial SRAM-based FPGA

A lean FPGA soft processor built using a DSP block

EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)

Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)

Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only)

Communication visualization for bottleneck detection of high-level synthesis applications

A fast discrete placement algorithm for FPGAs

Functionally verifying state saving and restoration in dynamically reconfigurable systems

FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)

The VTR project: architecture and CAD for FPGAs from verilog to routing

Content Provider	ACM Digital Library
Author	Jamieson, Peter Anderson, Jason Somerville, Andrew Goeders, Jeffrey Densmore, Opal Rose, Jonathan Yu, Chi Wai Kent, Kenneth B. Luu, Jason
Abstract	To facilitate the development of future FPGA architectures and CAD tools -- both embedded programmable fabrics and pure-play FPGAs -- there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described hypothetical FPGA architectures. These circuits should be captured at the HDL level, or higher, and pass through logical and physical synthesis. Such a tool must provide detailed modelling of area, performance and energy to enable architecture exploration. As software flows themselves evolve to permit design capture at ever higher levels of abstraction, this downstream full-implementation flow will always be required. This paper describes the current status and new release of an ongoing effort to create such a flow - the 'Verilog to Routing' (VTR) project, which is a broad collaboration of researchers. There are three core tools: ODIN II for Verilog Elaboration and front-end hard-block synthesis, ABC for logic synthesis, and VPR for physical synthesis and analysis. ODIN II now has a simulation capability to help verify that its output is correct, as well as specialized synthesis at the elaboration step for multipliers and memories. ABC is used to optimize the 'soft' logic of the FPGA. The VPR-based packing, placement and routing is now fully timing-driven (the previous release was not) and includes new capability to target complex logic blocks. In addition we have added a set of four large benchmark circuits to a suite of previously-released Verilog HDL circuits. Finally, we illustrate the use of the new flow by using it to help architect a floating-point unit in an FPGA, and contrast it with a prior, much longer effort that was required to do the same thing.
Starting Page	77
Ending Page	86
Page Count	10
File Format	PDF
ISBN	9781450311557
DOI	10.1145/2145694.2145708
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Architecture Fpga Cad
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The VTR project: architecture and CAD for FPGAs from Verilog to routing (2012)

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

VTR 7.0: Next Generation Architecture and CAD System for FPGAs

6 vtr 7.0: next generation architecture and cad system (2014).

An accurate evaluation of routing density for symmetrical FPGAs

Runtime and quality tradeoffs in FPGA placement and routing

Improved language support for Verilog elaboration in Odin II and FPGA architecture benchmarking in the VTR CAD tool

A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS

Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only)

The VTR project: architecture and CAD for FPGAs from verilog to routing

Similar Documents

The VTR project: architecture and CAD for FPGAs from Verilog to routing (2012)

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

VTR 7.0: Next Generation Architecture and CAD System for FPGAs

6 vtr 7.0: next generation architecture and cad system (2014).

An accurate evaluation of routing density for symmetrical FPGAs

Runtime and quality tradeoffs in FPGA placement and routing

Improved language support for Verilog elaboration in Odin II and FPGA architecture benchmarking in the VTR CAD tool

A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS

Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only)

The VTR project: architecture and CAD for FPGAs from verilog to routing