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The VTR project: architecture and CAD for FPGAs from Verilog to routing (2012)
| Content Provider | CiteSeerX |
|---|---|
| Author | Rose, Jonathan Luu, Jason Yu, Chi Wai Densmore, Opal Goeders, Jeffrey Somerville, Andrew Kent, Kenneth B. Jamieson, Peter Anderson, Jason |
| Description | To facilitate the development of future FPGA architectures and CAD tools – both embedded programmable fabrics and pure-play FPGAs – there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described hypothetical FPGA architectures. These circuits should be captured at the HDL level, or higher, and pass through logical and physical synthesis. Such a tool must provide detailed modelling of area, performance and energy to enable architecture exploration. As software flows themselves evolve to permit design capture at ever higher levels of abstraction, this downstream full-implementation flow will always be required. This paper describes the current status and new release of an ongoing effort to create such a flow-the ‘Verilog to Routing ’ (VTR) project, which is a broad collaboration In ACM/SIGDA International Symposium on Field Programmable Gate Arrays |
| File Format | |
| Language | English |
| Publisher Date | 2012-01-01 |
| Access Restriction | Open |
| Subject Keyword | Downstream Full-implementation Flow Ongoing Effort Pure-play Fpgas Architecture Exploration Cad Tool Easily-described Hypothetical Fpga Architecture Vtr Project New Release Detailed Modelling Programmable Fabric Design Capture Physical Synthesis Broad Collaboration Flow-the Verilog Hdl Level Available Software Suite Current Status Large Scale Future Fpga Architecture |
| Content Type | Text |
| Resource Type | Article |
