NDLI: Maximum current estimation considering power gating

Please wait, while we are loading the content...

Differences in ASIC, COT and processor design (panel)

Buffered Steiner trees for difficult instances

An exact algorithm for coupling-free routing

RC(L) interconnect sizing with second order considerations via posynomial programming

A performance-driven standard-cell placer based on a modified force-directed algorithm

Reporting of standard cell placement results

Application of automated design migration to alternating phase shift mask design

Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs

Impact of RET on physical layouts

Design of robust global power and ground networks

Decoupling capacitance allocation for power supply noise suppression

Overview of continuous optimization advances and applications to circuit tuning

Design and analysis of physical design algorithms

Multi-GHz interconnect effects in microprocessors

Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead

Maximum current estimation considering power gating

Estimating routing congestion using probabilistic analysis

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process

Slicing floorplan design with boundary-constrained modules

A regularity-driven fast gridless detailed router for high frequency datapath designs

Revisiting floorplan representations

Consistent floorplanning with super hierarchical constraints

ECBL: an extended corner block list with solution space including optimum placement

Rectilinear block packing using O-tree representation

Congestion estimation during top-down placement

Interconnect characteristics of 2.5-D system integration scheme

Hierarchical physical design methodology for multi-million gate chips

Overcoming wireload model uncertainty during physical design

A minimum cost path search algorithm through tile obstacles

An exact algorithm for solving difficult detailed routing problems

Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters

Physical design for FPGAs

A comparative study of two Boolean formulations of FPGA detailed routing constraints

Analysis and optimization of thermal issues in high-performance VLSI

Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method

Maximum current estimation considering power gating

Content Provider	ACM Digital Library
Author	Li, Fei He, Lei
Abstract	As semiconductor technology scales down, the leakage power will soon become comparable to the dynamic power. To reduce both dynamic and leakage power, power gating in addition to clock gating should be used because clock gating saves only dynamic power. The knowledge of maximum current is needed to design high-performance and reliable circuits using power gating. However, all existing techniques for maximum current estimation are not applicable to power gating. In this paper, we study the maximum current estimation problem considering power gating. We develop two algorithms based on automatic test pattern generation (ATPG), and apply them to ISCAS'85 benchmarks. Experiments show that our new estimation algorithms can finish the largest benchmark circuit within ten seconds, and achieve up to 87% larger current when compared to an existing ATPG-based estimation algorithm that is able to obtain maximum current estimation 6% less than the theoretical maximum current without considering power gating. This implies that power gating may lead to a larger maximum current when compared to the normal maximum switching current, and open a new avenue for maximum current estimation as well as circuit reliability research.
Starting Page	106
Ending Page	111
Page Count	6
File Format	PDF
ISBN	1581133472
DOI	10.1145/369691.369748
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-04-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Atpg Power estimation Low-power design Power gating
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Maximum current estimation considering power gating (2001)

Estimation of maximum power-up current (2001)

Estimation of Maximum Power-up Current

Estimation of maximum power-up current (2001)

Physical design methodology of power gating circuits for standard-cell-based design

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs

Physical design methodology of power gating circuits for standard-cell-based design

An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs

Maximum current estimation considering power gating

Similar Documents

Maximum current estimation considering power gating (2001)

Estimation of maximum power-up current (2001)

Estimation of Maximum Power-up Current

Estimation of maximum power-up current (2001)

Physical design methodology of power gating circuits for standard-cell-based design

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs

Physical design methodology of power gating circuits for standard-cell-based design

An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs

Maximum current estimation considering power gating