NDLI: A performance-driven standard-cell placer based on a modified force-directed algorithm

Please wait, while we are loading the content...

Differences in ASIC, COT and processor design (panel)

Buffered Steiner trees for difficult instances

An exact algorithm for coupling-free routing

RC(L) interconnect sizing with second order considerations via posynomial programming

A performance-driven standard-cell placer based on a modified force-directed algorithm

Reporting of standard cell placement results

Application of automated design migration to alternating phase shift mask design

Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs

Impact of RET on physical layouts

Design of robust global power and ground networks

Decoupling capacitance allocation for power supply noise suppression

Overview of continuous optimization advances and applications to circuit tuning

Design and analysis of physical design algorithms

Multi-GHz interconnect effects in microprocessors

Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead

Maximum current estimation considering power gating

Estimating routing congestion using probabilistic analysis

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process

Slicing floorplan design with boundary-constrained modules

A regularity-driven fast gridless detailed router for high frequency datapath designs

Revisiting floorplan representations

Consistent floorplanning with super hierarchical constraints

ECBL: an extended corner block list with solution space including optimum placement

Rectilinear block packing using O-tree representation

Congestion estimation during top-down placement

Interconnect characteristics of 2.5-D system integration scheme

Hierarchical physical design methodology for multi-million gate chips

Overcoming wireload model uncertainty during physical design

A minimum cost path search algorithm through tile obstacles

An exact algorithm for solving difficult detailed routing problems

Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters

Physical design for FPGAs

A comparative study of two Boolean formulations of FPGA detailed routing constraints

Analysis and optimization of thermal issues in high-performance VLSI

Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method

A performance-driven standard-cell placer based on a modified force-directed algorithm

Content Provider	ACM Digital Library
Author	Lin, Youn-Long Chou, Yih-Chih
Abstract	We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified I/O pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move a cell to its force-balanced location assuming all other cells are fixed. The process stops when no cell can be moved farther than a threshold distance. Next, cell rows are adjusted one at a time starting from the top and bottom. After forming these two rows (top/bottom), all movable core cells force-balanced locations are updated. The row-formation-and-update process continues until all rows are adjusted and, hence, a legal placement is obtained. We have integrated the proposed approach into an industrial APR flow. Experimental results on benchmark circuits up to 191K-cell (500K-gate) show that the critical path delay can be improved by as much as 11.5%. We also study the effect on both layout quality and CPU time consumption due to the amount of pseudo net added. We found that the introduction of pseudo net indeed significantly improves the layout quality.
Starting Page	24
Ending Page	29
Page Count	6
File Format	PDF
ISBN	1581133472
DOI	10.1145/369691.369722
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-04-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Timing closure Placement Force-directed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in