NDLI: GPU register file virtualization

Please wait, while we are loading the content...

Large pages and lightweight memory management in virtualized environments: can you have it both ways?

HyComp: a hybrid cache compression method for selection of data-type-specific compression methods

Avoiding information leakage in the memory controller with fixed service policies

Efficiently prefetching complex address patterns

DeSC: decoupled supply-compute communication management for heterogeneous architectures

More is less: improving the energy efficiency of data movement via opportunistic use of sparse codes

The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU

DynaMOS: dynamic schedule migration for heterogeneous cores

SAWS: synchronization aware GPGPU warp scheduling for multiple independent warp schedulers

Ultra-low power render-based collision detection for CPU/GPU systems

Prediction-guided performance-energy trade-off for interactive applications

Modeling the implications of DRAM failures and protection techniques on datacenter TCO

CLEAN-ECC: high reliability ECC for adaptive granularity memory system

Efficient GPU synchronization without scopes: saying no to complex consistency models

Characterizing, modeling, and improving the QoE of mobile devices with low battery level

Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems

Doppelgänger: a cache for approximate computing

Fork path: improving efficiency of ORAM by removing redundant memory accesses

Self-contained, accurate precomputation prefetching

Efficient warp execution in presence of divergence with collaborative context collection

Improving DRAM latency with dynamic asymmetric subarray

Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach

Long term parking (LTP): criticality-aware resource allocation in OOO processors

Enabling coordinated register allocation and thread-level parallelism optimization for GPUs

Execution time prediction for energy-efficient hardware accelerators

Architecture-aware automatic computation offload for native applications

TimeTrader: exploiting latency tail to save datacenter energy for online search

vCache: architectural support for transparent and isolated virtual LLCs in virtualized environments

Efficient persist barriers for multicores

Cross-architecture performance prediction (XAPP) using CPU code to predict GPU performance

CCICheck: using µhb graphs to verify the coherence-consistency interface

The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory

Locking down insecure indirection with hardware-based control-data isolation

Confluence: unified instruction supply for scale-out servers

Control flow coalescing on a hybrid dataflow/von Neumann GPGPU

Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses

Adaptive guardband scheduling to improve system-level efficiency of the POWER7+

The inner most loop iteration counter: a new dimension in branch history

Free launch: optimizing GPU dynamic kernel launches through thread reuse

Border control: sandboxing accelerators

Fast support for unstructured data processing: the unified automata processor

Rubik: fast analytical power management for latency-critical systems

An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors

ThyNVM: enabling software-transparent crash consistency in persistent memory systems

A fast and accurate analytical technique to compute the AVF of sequential bits in a processor

MORC: a manycore-oriented compressed cache

Authenticache: harnessing cache ECC for system authentication

IMP: indirect memory prefetcher

A scalable architecture for ordered parallelism

Filtered runahead execution with a runahead buffer

GPU register file virtualization

Neural acceleration for GPU throughput processors

Enabling interposer-based disintegration of multi-core processors

Coherence domain restriction on large scale systems

Enabling portable energy efficiency with memory accelerated library

Bungee jumps: accelerating indirect branches through HW/SW co-design

WarpPool: sharing requests with inter-warp coalescing for throughput processors

Neuromorphic accelerators: a comparison between neuroscience and machine-learning approaches

DCS: a fast and scalable device-centric server architecture

Efficiently enforcing strong memory ordering in GPUs

Microarchitectural implications of event-driven server-side web applications

GPU register file virtualization

Content Provider	ACM Digital Library
Author	Annavaram, Murali Ravi, Gokul Subramanian Kim, Nam Sung Jeon, Hyeran
Abstract	To support massive number of parallel thread contexts, Graphics Processing Units (GPUs) use a huge register file, which is responsible for a large fraction of GPU's total power and area. The conventional belief is that a large register file is inevitable for accommodating more parallel thread contexts, and technology scaling makes it feasible to incorporate ever increasing size of register file. In this paper, we demonstrate that the register file size need not be large to accommodate more threads context. We first characterize the useful lifetime of a register and show that register lifetimes vary drastically across various registers that are allocated to a kernel. While some registers are alive for the entire duration of the kernel execution, some registers have a short lifespan. We propose GPU register file virtualization that allows multiple warps to share physical registers. Since warps may be scheduled for execution at different points in time, we propose to proactively release dead registers from one warp and re-allocate them to a different warp that may occur later in time, thereby reducing the needless demand for physical registers. By using register virtualization, we shrink the architected register space to a smaller physical register space. By under-provisioning the physical register file to be smaller than the architected register file we reduce dynamic and static power consumption. We then develop a new register throttling mechanism to run applications that exceed the size of the under-provisioned register file without any deadlock. Our evaluation shows that even after halving the architected register file size using our proposed GPU register file virtualization applications run successfully with negligible performance overhead.
Starting Page	420
Ending Page	432
Page Count	13
File Format	PDF
ISBN	9781450340342
DOI	10.1145/2830772.2830784
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-12-05
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Register file Microarchitecture Energy-efficient computing Gpgpu
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

GPGPU Task Scheduling Technique for Reducing the Performance Deviation of Multiple GPGPU Tasks in RPC-Based GPU Virtualization Environments

An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU

SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading

ARGO: aging-aware GPGPU register file allocation

An evaluation of CUDA-enabled virtualization solutions

Adaptive Cache Management for Energy-Efficient GPU Computing

Integrating nanophotonics in GPU microarchitecture

Warped register file: A power efficient register file for GPGPUs

GPU register file virtualization

Similar Documents

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

GPGPU Task Scheduling Technique for Reducing the Performance Deviation of Multiple GPGPU Tasks in RPC-Based GPU Virtualization Environments

An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU

SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading

ARGO: aging-aware GPGPU register file allocation

An evaluation of CUDA-enabled virtualization solutions

Adaptive Cache Management for Energy-Efficient GPU Computing

Integrating nanophotonics in GPU microarchitecture

Warped register file: A power efficient register file for GPGPUs

GPU register file virtualization