NDLI: NBTI tolerant microarchitecture design in the presence of process variation

Content Provider	ACM Digital Library
Author	Fortes, Jose
Abstract	Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Parametric variation introduced by nano-scale device fabrication inaccuracy can exacerbate the PMOS transistor wear-out problem and further reduce the reliable lifetime of microprocessors. In this work, we propose microarchitecture design techniques to combat the combined effect of NBTI and process variation (PV) on the reliability of high-performance microprocessors. Experimental evaluation shows our proposed process variation aware (PV-aware) NBTI tolerant microarchitecture design techniques can considerably improve the lifetime of reliability operation while achieving an attractive trade-off with performance and power.
Starting Page	399
Ending Page	410
Page Count	12
File Format	PDF
ISBN	9781424428366
DOI	10.1109/MICRO.2008.4771808
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-11-08
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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NBTI tolerant microarchitecture design in the presence of process variation