NDLI: Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening

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Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening

Content Provider	ACM Digital Library
Author	Vendraminetto, D. Palena, M. Camurati, P. E. Pasini, P. Cabodi, G.
Abstract	We address the problem of reducing the size of Craig interpolants used in SAT-based Model Checking. Craig interpolants are AND-OR circuits, generated by post-processing refutation proofs of SAT solvers. Whereas it is well known that interpolants are highly redundant, their compaction is typically tackled by reducing the proof graph and/or by exploiting standard logic synthesis techniques. Furthermore, strengthening and weakening have been studied as an option to control interpolant quality. In this paper we propose two interpolant compaction techniques: (1) A set of ad-hoc logic synthesis functions that, revisiting known logic synthesis approaches, specifically address speed and scalability. Though general and not restricted to interpolants, these techniques target the main sources of redundancy in interpolant circuits. (2) An interpolant weakening technique, where the UNSAT core extracted from an additional SAT query is used to obtain a gate-level abstraction of the interpolant. The abstraction introduces fresh new variables at gate cuts that must be quantified out in order to obtain a valid interpolant. We show how to efficiently quantify them out, by working on an NNF representation of the circuit. The paper includes an experimental evaluation, showing the benefits of the proposed techniques, on a set of benchmark interpolants arising from both hardware and software model checking problems.
Starting Page	25
Ending Page	32
Page Count	8
File Format	PDF
ISBN	9780983567868
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-10-03
Publisher Place	Austin
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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