NDLI: Low Vccmin fault-tolerant cache with highly predictable performance

Please wait, while we are loading the content...

POWER7 multi-core processor design

Characterizing and mitigating the impact of process variations on phase change based memory systems

Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping

Improving cache lifetime reliability at ultra-low voltages

BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support

Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures

Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

In-network coherence filtering: snoopy coherence without broadcasts

Why design must change: rethinking digital design

Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip

Coordinated control of multiple prefetchers in multi-core systems

Using a configurable processor generator for computer architecture prototyping

Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches

Tribeca: design for PVT variations with local recovery and fine-grained adaptation

McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

Optimizing shared cache behavior of chip multiprocessors

Light64: lightweight hardware support for data race detection during systematic testing of parallel programs

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage

ZerehCache: armoring cache architectures in high defect density technologies

EazyHTM: eager-lazy hardware transactional memory

A microarchitecture-based framework for pre- and post-silicon power delivery analysis

An hybrid eDRAM/SRAM macrocell to implement first-level data caches

SCARAB: a single cycle adaptive routing and bufferless network

Application-aware prioritization mechanisms for on-chip networks

Improving memory bank-level parallelism in the presence of prefetching

Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications

Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems

The BubbleWrap many-core: popping cores for sequential acceleration

Characterizing the resource-sharing levels in the UltraSPARC T2 processor

SHARP control: controlled shared cache management in chip multiprocessors

Finding concurrency bugs with context-aware communication graphs

Characterizing flash memory: anomalies, observations, and applications

Tree register allocation

Low Vccmin fault-tolerant cache with highly predictable performance

Proactive transaction scheduling for contention management

Reducing peak power with a table-driven adaptive processor core

Variation-tolerant non-uniform 3D cache management in die stacked multicore processor

Low-cost router microarchitecture for on-chip networks

A case for dynamic frequency tuning in on-chip networks

ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem

Ordering decoupled metadata accesses in multiprocessors

A tagless coherence directory

Multiple clock and voltage domains for chip multi processors

Execution leases: a hardware-supported mechanism for enforcing strong non-interference

Adaptive line placement with the set balancing cache

Offline symbolic analysis for multi-processor execution replay

Complexity effective memory access scheduling for many-core accelerator architectures

Portable compiler optimisation across embedded programs and microarchitectures using machine learning

mSWAT: low-cost hardware fault detection and diagnosis for multicore systems

Light speed arbitration and flow control for nanophotonic interconnects

Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance

Control flow obfuscation with information flow tracking

Architecting a chunk-based memory race recorder in modern CMPs

Low Vccmin fault-tolerant cache with highly predictable performance

Content Provider	ACM Digital Library
Author	Carretero, Javier Chaparro, Pedro Vera, Xavier González, Antonio Abella, Jaume
Abstract	Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent excessive degradation and keep power demand within reasonable limits. Unfortunately, low Vcc operation exacerbates the effect of variations and decreases noise and stability margins, increasing the likelihood of errors in SRAM memories such as caches. Those errors translate into performance loss and performance variation across different cores, which is especially undesirable in a multi-core processor. This paper presents (i) a novel scheme to tolerate high faulty bit rates in caches by disabling only faulty subblocks, (ii) a dynamic address remapping scheme to reduce performance variation across different cores, which is key for performance predictability, and (iii) a comparison with state-of-the-art techniques for faulty bit tolerance in caches. Results for some typical first level data cache configurations show 15% average performance increase and standard deviation reduction from 3.13% down to 0.55% when compared to cache line disabling schemes.
Starting Page	111
Ending Page	121
Page Count	11
File Format	PDF
ISBN	9781605587981
DOI	10.1145/1669112.1669128
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-12-12
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Faults Predictable performance Vccmin Cache
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in