NDLI: Controller estimation for FPGA target architectures during high-level synthesis

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Controller estimation for FPGA target architectures during high-level synthesis

Content Provider	ACM Digital Library
Author	Bringmann, Oliver Rosenstiel, Wolfgang Menn, Carsten
Abstract	In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence, especially, if a certain data-path realization requires a huge number of states and/or con trol signals. This paper presents a new approach on controller estimation during high-level synthesis for FPGA-based target architectures. The estimator, presented in this paper can be invoked after or during every synthesis-step, i.e. allocation, scheduling and binding, respectively. By considering the control ler influence on the overall area of a design, design space explo ration can be made more accurate and less error prone. We present an approach for estimating area of the controller based on information which are easily accessible during each step of high-level synthesis, so no explicit description of the controller, which usually will be generated after the binding, is necessary. This is particularly valuable in the allocation phase, where intensive design space explorations have to be done, based on fast and accurate estimates.
Starting Page	56
Ending Page	61
Page Count	6
File Format	PDF
ISBN	1581135769
DOI	10.1145/581199.581213
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-10-02
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Area estimation High-level synthesis Fpga Controller
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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