NDLI: Minimum area retiming with equivalent initial states

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Conference Committee

Technical Program Committee

Tutorial 1: Timing Analysis and Optimization: From Devices to Systems

Tutorial 2: Design Technology for Building Wireless Systems

Tutorial 3: Modeling and Synthesis of Behavior, Control and Dataflow

Tutorial 4: Critical Technologies and Methodologies for Systems-On-Chips

Keynote Address

PHDD: an efficient graph representation for floating point circuit verification

Functional simulation using binary decision diagrams

Generalized matching from theory to application

Decomposition of timed decision tables and its use in presynthesis optimizations

A predictive system shutdown method for energy saving of event-driven computation

Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems

Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs

Effects of delay models on peak power estimation of VLSI sequential circuits

COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits

PRIMA: passive reduced-order interconnect macromodeling algorithm

A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks

Multipoint Padé approximation using a rational block Lanczos algorithm

The disjunctive decomposition of logic functions

Speeding up technology-independent timing optimization by network partitioning

Negative thinking by incremental problem solving: application to unate covering

DSP address optimization using a minimum cost circulation technique

Application-driven synthesis of core-based systems

Power optimization using divide-and-conquer techniques for minimization of the number of operations

High-level area and power estimation for VLSI circuits

Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems

Achievable bounds on signal transition activity

Circuit noise evaluation by Padé approximation based model-reduction techniques

Global harmony: coupled noise analysis for full-chip RC interconnect networks

Efficient coupled noise estimation for on-chip interconnects

Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits

Verifying correct pipeline implementation for microprocessors

A quantitative approach to functional debugging

Approximate timing analysis of combinational circuits under the XBD0 model

Timing analysis based on primitive path delay fault identification

Approximate algorithms for time separation of events

Optimization techniques for high-performance digital circuits

Sequential optimisation without state space exploration

Minimum area retiming with equivalent initial states

Decomposition and technology mapping of speed-independent circuits using Boolean relations

Scheduling and binding bounds for RT-level symbolic execution

High-level scheduling model and control synthesis for a broad range of design applications

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions

Optimal wire and transistor sizing for circuits with non-tree topology

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

A hierarchical decomposition methodology for multistage clock circuits

A new high-order absolutely-stable explicit numerical integration algorithm for the time-domain simulation of nonlinear circuits

Circuit optimization via adjoint Lagrangians

State transformation in event driven explicit simulation

A fast and robust exact algorithm for face embedding

An output encoding problem and a solution technique

OPTIMIST: state minimization for optimal 2-level logic implementation

Resource sharing in hierarchical synthesis

Generalized resource sharing

Exploiting off-chip memory access modes in high-level synthesis

Replication for logic bipartitioning

Partitioning around roadblocks: tackling constraints with intermediate relaxations

Adaptive methods for netlist partitioning

Symbolic analysis of large analog circuits with determinant decision diagrams

A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps

Test generation for comprehensive testing of linear analog circuits using transient response sampling

Reachability analysis using partitioned-ROBDDs

Record & play: a structural fixed point iteration for sequential circuit verification

Forward model checking techniques oriented to buggy designs

BIST TPG for faults in system backplanes

A test synthesis technique using redundant register transfers

Built-in test generation for synchronous sequential circuits

Hierarchical partitioning for field-programmable systems

Hybrid spectral/iterative partitioning

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

IES3: a fast integral equation solver for efficient 3-dimensional extraction

FastPep: a fast parasitic extraction program for complex three-dimensional geometries

Transform domain techniques for efficient extraction of substrate parasitics

EDA and the network

Interconnect design for deep submicron ICs

Accurate power estimation for large sequential circuits

Fast power estimation for deterministic input streams

A power modeling and characterization method for macrocells using structure information

Transformational partitioning for co-design of multiprocessor systems

Hardware/software partitioning for multi-function systems

MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems

NRG: global and detailed placement

Simulated quenching: a new placement method for module generation

A signature based approach to regularity extraction

Fault simulation of interconnect opens in digital CMOS circuits

GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment

A deductive technique for diagnosis of bridging faults

Low power logic synthesis for XOR based circuits

An exact gate decomposition algorithm for low-power technology mapping

Trace driven logic synthesis—application to power minimization

Performance analysis of a system of communicating processes

Embedded program timing analysis based on path clustering and architecture classification

Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system

A new approach to simultaneous buffer insertion and wire sizing

Optimal shape function for a bi-directional wire under Elmore delay model

Global interconnect sizing and spacing with consideration of coupling capacitance

Test generation for primitive path delay faults in combinational circuits

Fast identification of untestable delay faults using implications

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists

Library-less synthesis for static CMOS combinational logic circuits

Logic synthesis for large pass transistor circuits

An exact solution to simultaneous technology mapping and linear placement problem

An efficient statistical analysis methodology and its application to high-density DRAMs

Fast field solver-programs for thermal and electrostatic analysis of microsystem elements

Java as a specification language for hardware-software systems

Post-route optimization for improved yield using a rubber-band wiring model

Delay bounded buffered tree construction for timing driven floorplanning

Interconnect layout optimization under higher-order RLC model

Test and diagnosis of fault logic blocks in FPGAs

Partial scan delay fault testing of asynchronous circuits

Maximum independent sets on transitive graphs and their applications in testing and CAD

Verifying hardware in its software context

Simulation methods for RF integrated circuits

Timing analysis and optimization (tutorial): from devices to systems

Critical technologies and methodologies for systems-on-chips (tutorial)

Modeling and synthesis of behavior, control and dataflow (tutorial)

Design technology for building wireless systems (tutorial)

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