NDLI: Partial scan delay fault testing of asynchronous circuits

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Partial scan delay fault testing of asynchronous circuits

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Partial scan delay fault testing of asynchronous circuits

Content Provider	ACM Digital Library
Author	Kishinevsky, Michael Taubin, Alexander Saldanha, Alexander Kondratyev, Alex Lavagno, Luciano
Abstract	Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect possible delay faults in a sequential asynchronous circuit. The delays that are to be tested must be provided by the synthesis system. By using this information a set of paths in the circuit that must be tested is identified (step 1). For these paths the circuit is made acyclic by inserting at least one scan latch in every cycle (step 2). Then test patterns are generated for these paths (step 3). These test patterns consist of setup and initialization vectors and the final test vector. We provide effective procedures to solve both the initialization and the test pattern generation problem. The latter problem is solved by reduction to a classical problem of stuck-at test pattern generation for a related combinational circuit. Finally, a heuristic is proposed to determine which state variables must become part of a scan chain, or for which input variables the positive and negative phase must be driven independently in test mode. Experimental results shows that a high level of path delay fault testability can be achieved with partial scan.
Starting Page	728
Ending Page	735
Page Count	8
File Format	PDF
ISBN	0818682000
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1997-11-13
Access Restriction	Subscribed
Subject Keyword	Delay faults sequential testing asynchronous circuits robust path delay fault testing
Content Type	Text
Resource Type	Article

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