NDLI: Exploring hybrid memory for GPU energy efficiency through software-hardware co-design

Please wait, while we are loading the content...

A comprehensive approach to HW/SW codesign

INSPIRE: the insieme parallel intermediate representation

ThermOS: system support for dynamic thermal management of chip multi-processors

APOGEE: adaptive prefetching on GPUs for energy efficiency

S-CAVE: effective SSD caching to improve virtual machine storage performance

A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

Fairness-aware scheduling on single-ISA heterogeneous multi-cores

Jigsaw: scalable software-defined caches

Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems

The case for a scalable coherence protocol for complex on-chip cache hierarchies in many core systems

Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect

Vectorization past dependent branches through speculation

TCPT: thread criticality-driven prefetcher throttling

Parallel programming for mobile computing

Parallel flow-sensitive pointer analysis by graph-rewriting

Coordinated power-performance optimization in manycores

Parallel frame rendering: trading responsiveness for energy on a mobile GPU

Writeback-aware bandwidth partitioning for multi-core systems with PCM

Memory-centric system interconnect design with hybrid memory cubes

DANBI: dynamic scheduling of irregular stream programs for many-core systems

Managing shared last-level cache in a heterogeneous multicore processor

Starchart: hardware and software optimization using recursive partitioning regression trees

Meeting midway: improving CMP performance with memory-side prefetching

McRouter: multicast within a router for high performance network-on-chips

Automatic vectorization of tree traversals

Do inputs matter?: using data-dependence profiling to evaluate thread level speculation in BG/Q

Towards automatic resource management in parallel architectures

Interprocedural strength reduction of critical sections in explicitly-parallel programs

An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs

Exploring hybrid memory for GPU energy efficiency through software-hardware co-design

L1-bandwidth aware thread allocation in multicore SMT processors

Neither more nor less: optimizing thread-level parallelism for GPGPUs

An empirical model for predicting cross-core performance interference on multicore processors

Reshaping cache misses to improve row-buffer locality in multicore systems

RSVM: a region-based software virtual memory for GPU

Building expressive, area-efficient coherence directories

Concurrent predicates: a debugging technique for every parallel programmer

Generating efficient data movement code for heterogeneous architectures with distributed-memory

Can lock-free and combining techniques co-exist?: a novel approach on concurrent queue

SMT-centric power-aware thread placement in chip multiprocessors

Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG

Automatic OpenCL work-group size selection for multicore CPUs

Task sampling: computer architecture simulation in the many-core era

PS-cache: an energy-efficient cache design for chip multiprocessors

Dynamic memory access monitoring based on tagged memory

Exposing ILP in custom hardware with a dataflow compiler IR

Exploring hybrid memory for GPU energy efficiency through software-hardware co-design

Content Provider	ACM Digital Library
Author	Yu, Weikuan Wang, Bin Li, Dong Wu, Bo Jiao, Yizheng Vetter, Jeffrey S. Shen, Xipeng
Abstract	Hybrid memory designs, such as DRAM plus Phase Change Memory (PCM), have shown some promise for alleviating power and density issues faced by traditional memory systems. But previous studies have concentrated on CPU systems with a modest level of parallelism. This work studies the problem in a massively parallel setting. Specifically, it investigates the special implications to hybrid memory imposed by the massive parallelism in GPU. It empirically shows that, contrary to promising results demonstrated for CPU, previous designs of PCM-based hybrid memory result in significant degradation to the energy efficiency of GPU. It reveals that the fundamental reason comes from a multi-facet mismatch between those designs and the massive parallelism in GPU. It presents a solution that centers around a close cooperation between compiler-directed data placement and hardware-assisted runtime adaptation. The co-design approach helps tap into the full potential of hybrid memory for GPU without requiring dramatic hardware changes over previous designs, yielding 6% and 49% energy saving on average compared to pure DRAM and pure PCM respectively, and keeping performance loss less than 2%.
Starting Page	93
Ending Page	102
Page Count	10
File Format	PDF
ISBN	9781479910212
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-10-07
Access Restriction	Subscribed
Subject Keyword	Co-design Nvram Energy efficiency Gpu
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in