NDLI: Proceedings of the 22nd international conference on Parallel architectures and compilation techniques (PACT '13)

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A comprehensive approach to HW/SW codesign

INSPIRE: the insieme parallel intermediate representation

ThermOS: system support for dynamic thermal management of chip multi-processors

APOGEE: adaptive prefetching on GPUs for energy efficiency

S-CAVE: effective SSD caching to improve virtual machine storage performance

A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors

Fairness-aware scheduling on single-ISA heterogeneous multi-cores

Jigsaw: scalable software-defined caches

Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems

The case for a scalable coherence protocol for complex on-chip cache hierarchies in many core systems

Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect

Vectorization past dependent branches through speculation

TCPT: thread criticality-driven prefetcher throttling

Parallel programming for mobile computing

Parallel flow-sensitive pointer analysis by graph-rewriting

Coordinated power-performance optimization in manycores

Parallel frame rendering: trading responsiveness for energy on a mobile GPU

Writeback-aware bandwidth partitioning for multi-core systems with PCM

Memory-centric system interconnect design with hybrid memory cubes

DANBI: dynamic scheduling of irregular stream programs for many-core systems

Managing shared last-level cache in a heterogeneous multicore processor

Starchart: hardware and software optimization using recursive partitioning regression trees

Meeting midway: improving CMP performance with memory-side prefetching

McRouter: multicast within a router for high performance network-on-chips

Automatic vectorization of tree traversals

Do inputs matter?: using data-dependence profiling to evaluate thread level speculation in BG/Q

Towards automatic resource management in parallel architectures

Interprocedural strength reduction of critical sections in explicitly-parallel programs

An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs

Exploring hybrid memory for GPU energy efficiency through software-hardware co-design

L1-bandwidth aware thread allocation in multicore SMT processors

Neither more nor less: optimizing thread-level parallelism for GPGPUs

An empirical model for predicting cross-core performance interference on multicore processors

Reshaping cache misses to improve row-buffer locality in multicore systems

RSVM: a region-based software virtual memory for GPU

Building expressive, area-efficient coherence directories

Concurrent predicates: a debugging technique for every parallel programmer

Generating efficient data movement code for heterogeneous architectures with distributed-memory

Can lock-free and combining techniques co-exist?: a novel approach on concurrent queue

SMT-centric power-aware thread placement in chip multiprocessors

Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG

Automatic OpenCL work-group size selection for multicore CPUs

Task sampling: computer architecture simulation in the many-core era

PS-cache: an energy-efficient cache design for chip multiprocessors

Dynamic memory access monitoring based on tagged memory

Exposing ILP in custom hardware with a dataflow compiler IR

Proceedings of the 22nd international conference on Parallel architectures and compilation techniques (PACT '13)

Content Provider	ACM Digital Library
Editor	Seznec, André Fensch, Christian O'Boyle, Michael Bodin, François
Copyright Year	2013
Abstract	It is an honor to introduce the technical program for the 22nd International Conference on Parallel Architectures and Compilation Techniques. The conference has become a premier forum for presenting new contributions in computer architecture and compiler technology. It allows both communities to interact and exchange. PACT 2013 received 208 paper submissions which is almost exactly the same number for the two previous years. These papers were handled by a PC committee of 47 members. Each PC member was personally responsible for his/her reviews. We did not use external reviewers. This year, we implemented a two passes double blind review process. In the first pass, the paper was reviewed by 3 PC committee members. Then the authors had the opportunity to react through the rebuttal. After the rebuttal, each paper was assigned to an extra PC member, the advocate. The role of the advocate was crucial in the review process. The advocate had to read the reviews, the rebuttal and skim through the paper. When there was a clear consensus on the outcome of the reviews, the advocate validated the consensus. When there was no clear consensus, the advocate wrote a new review and often triggered an on-line discussion. This often allowed to reach a consensus before the PC meeting in either the accept or the reject category. Thanks to John Cavazos, we held the PC meeting on the nice campus of University of Delaware on May 9. Due to diligent work of the whole committee before the meeting, we were able to reduce the maximum number of papers that could be discussed to 77. Moreover, we decided to concentrate the discussion on the controversial papers. The 22 papers with a clear accept consensus were accepted without discussion, 38 papers with no consensus were discussed and 17 papers with an average reject grade but with a strong defender were given a chance to be revived. We finally accepted 36 high quality papers (17% acceptance rate). We are particularly proud of the variety of the program with papers originating from the USA, China, Japan, Korea, India, Austria, Italy, Belgium and covering the whole spectrum of topics addressed by our communities.
ISBN	9781479910212
Language	English
Publisher	IEEE Press
Publisher Date	2013-10-07
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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