NDLI: Splitting functions into single-entry regions

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Splitting functions into single-entry regions

Content Provider	ACM Digital Library
Author	Brandner, Florian Hepp, Stefan
Abstract	As the performance requirements of today's real-time systems are on the rise, system engineers are increasingly forced to optimize and tune the execution time of real-time software. Apart from usual optimizations targeting the average-case performance of a program, the worst-case execution time bound (WCET) delivered by program analysis tools often has to be improved to meet all the deadlines and ensure a safe operation of the entire system. Modern computer architectures pose a significant challenge to this task due to their high complexity. Out-of-order execution, speculation, caches, buffers, and branch predictors highly depend on the execution history and are thus difficult to analyze precisely for WCET analysis tools. Time-predictable computer architectures overcome this problems by specifically designed hardware components that are amenable to static program analysis. A recently proposed alternative for caching executable code, i.e., instructions, is the so-called method cache. Instead of a traditional block-based cache design, the method cache operates on larger code blocks under the control of the compiler. Due to its design, the analysis of the method cache is simplified. At the same time, such a system now highly depends on the compiler and its ability to form suitable code blocks for caching. We propose a simple function splitting technique that derives a suitable partitioning of the basic blocks in a program, targeting the method cache of the time-predictable processor Patmos. Our approach exploits dominance properties to form code regions respecting the method cache's parameters as well as constraints of Patmos' instruction set architecture. Experimental results show that the method cache can be competitive with typical instruction cache configurations given the right splitting.
Starting Page	1
Ending Page	10
Page Count	10
File Format	PDF
ISBN	9781450330503
DOI	10.1145/2656106.2656128
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-10-12
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Graph partitioning Single-entry region Method cache Real-time systems Function splitting
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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