NDLI: Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

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Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators

Age-aware Logic and Memory Co-Placement for RRAM-FPGAs

Multi-variable Dynamic Power Management for the GPU Subsystem

Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns

3 Channel Dependency-Based Power Model for Mobile AMOLED Displays

Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture

Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking

Secure Information Flow Verification with Mutable Dependent Types

Ultra-Efficient Processing In-Memory for Data Intensive Applications

RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks

Toggle MUX: How X-Optimism Can Lead to Malicious Hardware

XFC: A Framework for eXploitable Fault Characterization in Block Ciphers

FFD: A Framework for Fake Flash Detection

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning

Coupled circuit/EM simulation for radio frequency circuits

Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements

Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits

ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited

Extensibility-Driven Automotive In-Vehicle Architecture Design: Invited

PriSearch: Efficient Search on Private Data

Extensibility in Automotive Security: Current Practice and Challenges: Invited

An Architecture for Learning Stream Distributions with Application to RNG Testing

Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited

Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in Hardware

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups

TraPL: Track Planning of Local Congestion for Global Routing

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs

Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead

Concurrent Pin Access Optimization for Unidirectional Routing

Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems

Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays

Deep Reinforcement Learning for Building HVAC Control

SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems

No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement

Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming

LO-FAT: Low-Overhead Control Flow ATtestation in Hardware

VirtualGC: Enabling Erase-free Garbage Collection to Upgrade the Performance of Rewritable SLC NAND Flash Memory

Analyzing Hardware Based Malware Detectors

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks

Instruction-Level Data Isolation for the Kernel on ARM

FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs

RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks

A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model

A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks

Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs

Optimized Design of a Human Intranet Network

Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: Invited

ArchEx: An Extensible Framework for the Exploration of Cyber-Physical System Architectures

EDiFy: An Execution time Distribution Finder

INVITED Challenges and Potential for Incorporating Model-Based Design in Medical Device Development: Extended Abstract

Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR

Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery

ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited

Template Aware Coverage: Taking Coverage Analysis to the Next Level

Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited

Test Methodology for Dual-rail Asynchronous Circuits

A-TEAM: Automatic template-based assertion miner

Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique

Hierarchical Dataflow Modeling of Iterative Applications

A New Paradigm for Synthesis of Linear Decompressors

InCheck: An In-application Recovery Scheme for Soft Errors

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect

Towards Aging-Induced Approximations

Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems

QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders

Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture

Bandwidth Optimization Through On-Chip Memory Restructuring for HLS

Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power Microcontrollers

Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM

Energy-Efficient Execution for Repetitive App Usages on big.LITTLE Architectures

DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis

HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors

Estimation of Safe Sensor Measurements of Autonomous System Under Attack

Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications

Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management

Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage

Crossroads: Time-Sensitive Autonomous Intersection Management Technique

A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes

Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs

On Quality Trade-off Control for Approximate Computing Using Iterative Training

On Characterizing Near-Threshold SRAM Failures in FinFET Technology

Fogging Effect Aware Placement in Electron Beam Lithography

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation

Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization

Making DRAM Stronger Against Row Hammering

Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation

A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment

Accelerator Design for Deep Learning Training: Extended Abstract: Invited

An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers

Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks

Dadu: Accelerating Inverse Kinematics for High-DOF Robots

Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation

Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User Detection

A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond

Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning

Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning

A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications

Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification

Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation

iClaire: A Fast and General Layout Pattern Classification Algorithm

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading

LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs

Power-aware Performance Tuning of GPU Applications Through Microbenchmarking

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations

A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits

Low-overhead Aging-aware Resource Management on Embedded GPUs

Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs

A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification

Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear Circuits

A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited

Retiming of Two-Phase Latch-Based Resilient Circuits

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design

Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution

Graph-Based Logic Bit Slicing for Datapath-Aware Placement

A Clock Tree Optimization Framework with Predictable Timing Quality

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits

Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits

Optimal Circuits for Parallel Bit Reversal

LiveSynth: Towards an Interactive Synthesis Flow

Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera System

Statistical Error Analysis for Low Power Approximate Adders

An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction

CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing

Pauli Frames for Quantum Computer Architectures

Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing

Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length

Hierarchical Reversible Logic Synthesis Using LUTs

Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

Detailed Placement for Two-Dimensional Directed Self-Assembly Technology

Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture

HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs

Statistical Pattern Based Modeling of GPU Memory Access Streams

Hardware ODE Solvers using Stochastic Circuits

A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability

ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: Invited

Specification, Verification and Design of Evolving Automotive Software: Invited

Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic

Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques

Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks

MOCA: an Inter/Intra-Chip Optical Network for Memory

Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System

Rescuing Memristor-based Neuromorphic Design with High Defects

Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems

Task Mapping on SMART NoC: Contention Matters, Not the Distance

Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC

Network Synthesis for Database Processing Units

Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

Content Provider	ACM Digital Library
Author	Kim, Taemin Zuo, Wei Pouchet, Louis-Noel Chen, Deming Lin, Chung-Wei Shiraishi, Shinichi Ayupov, Andrey
Abstract	A desirable feature of a development tool for SoC design is that, given the important applications in the domain to be targeted by the SoC, a powerful hardware-software partitioning engine is available to determine which function(s) shall be mapped to hardware. However, to provide high-quality partitioning, this engine must be able to consider a rich design space of possible alternate hardware and software implementations for each program region candidate for hardware acceleration, in turn making the task of finding the optimal mapping very difficult given the number of design points to consider and the need for accurate modeling of latency, power and area. In this work we propose a novel framework to enable hardware acceleration of performance-critical parts of an application, by addressing the problem of hardware/software partitioning under power and area constraints to minimize the overall program latency. Our flow is based on the LLVM compiler, and focuses on building a scalable compile-time partitioning algorithm while considering large sets of alternative hardware and software implementations for a particular region. To this end we develop a hybrid approach based on mixing semi-random selection of hardware design points and an Integer Linear Programming formulation of the mapping decision, along with iterative refinements of the solution. Experimental results demonstrate the capability of our approach to consider complex designs and yet output near-optimal partitioning decision. Our package is named RIP (Randomized ILP-based Partitioning), and is open source to benefit the research community.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450349277
DOI	10.1145/3061639.3062195
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-06-18
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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