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4b-2 flexible and executable hardware/software interface modeling for multiprocessor soc design using systemc.
| Content Provider | CiteSeerX |
|---|---|
| Author | Gerin, Patrice Shen, Hao Chureau, Alexandre Bouchhima, Aimen Jerraya, Ahmed Amine |
| Abstract | Abstract – At high abstraction level, Multi-Processor System-On-Chip (SoC) designs are specified as assembling of IP’s which can be Hardware or Software. The refinement of communication between these different IP’s, known as hardware/software interfaces, is widely seen as the design bottleneck due to their complexity. In order to perform early design validation and architecture exploration, flexible executable models of these interfaces are needed at different abstraction levels. In this paper, we define a unified methodology to implement executable models of the hardware/software interface based on SystemC. The proposed formalism based on the concept of services gives to this approach the flexibility needed for architecture exploration and the ability to be used in automatic generation tools. A case study of hardware/software interface modeling at the Transaction Accurate level is presented. Experimental results show that this method allows higher simulation speed with early performance estimation. I |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | 4b-2 Flexible Multiprocessor Soc Design Using Systemc Executable Hardware Software Interface Modeling Hardware Software Interface Architecture Exploration High Abstraction Level Transaction Accurate Level Multi-processor System-on-chip Executable Model Simulation Speed Flexible Executable Model Different Ip Early Performance Estimation Case Study Different Abstraction Level Unified Methodology Hardware Software Interface Modeling Early Design Validation Experimental Result Automatic Generation Tool Design Bottleneck |
| Content Type | Text |
