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| Content Provider | ACM Digital Library |
|---|---|
| Author | Shen, Ting-Yu Huang, Kuan-Yen Li, Chien-Mo |
| Abstract | With low power and variation-tolerant features, asynchronous have been widely used in advanced VLSI designs. Testing asynchronous circuits has become a very important practical issue. This research presents new test methodology, including design for testability (DFT) and automatic test pattern generation (ATPG), for asynchronous dual-rail circuits. The proposed DAC-scan cell is a hazard-free scan design, which can be applied to various implementations of dual-rail asynchronous circuits. Two-pattern stuck-at test and three-pattern delay test techniques are presented to detect local feedback faults in the circuits without inserting extra DFT into feedback loops. With our test methodology, we can use traditional full-scan ATPG to generate high fault coverage test patterns. Moreover, designers can tradeoff between fault coverage and area overhead by using different versions of DAC-scan cells. |
| Starting Page | 1 |
| Ending Page | 6 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781450349277 |
| DOI | 10.1145/3061639.3062325 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2017-06-18 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Automatic test pattern generation Design for testability Dual-rail Asynchronous circuits |
| Content Type | Text |
| Resource Type | Article |
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