NDLI: Block value based insertion policy for high performance last-level caches

Please wait, while we are loading the content...

HPC for the human brain project

LAWS: locality-aware work-stealing for multi-socket multi-core architectures

DTail: a flexible approach to DRAM refresh management

Evaluation of methods to integrate analysis into a large-scale shock shock physics code

21st century computer architecture keynote at 2014 international conference on supercomputing (ICS)

MT-MPI: multithreaded MPI for many-core environments

An optimal distributed load balancing algorithm for homogeneous work units

Revealing applications' access pattern in collective I/O for cache management

Palm: easing the burden of analytical performance modeling

The future of supercomputing

Acceleration of derivative calculations with application to radial basis function: finite-differences on the intel mic architecture

Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects

Scaling up matrix computations on shared-memory manycore systems with 1000 CPU cores

Effective automatic computation placement and data allocation for parallelization of regular programs

Last-level cache deduplication

Input-adaptive parallel sparse fast fourier transform for stream processing

Implementing a classic: zero-copy all-to-all communication with mpi datatypes

Addressing bandwidth contention in SMT multicores through scheduling

Supporting storage configuration for I/O intensive workflows

An end-to-end analysis of file system features on sparse virtual disks

An efficient two-dimensional blocking strategy for sparse matrix-vector multiplication on GPUs

A performance perspective on energy efficient HPC links

Collective memory transfers for multi-core chips

On the conditions for efficient interoperability with threads: an experience with PGAS languages using cray communication domains

Block value based insertion policy for high performance last-level caches

Thread-cooperative, bit-parallel computation of levenshtein distance on GPU

Value influence analysis for message passing applications

An adaptive cross-architecture combination method for graph traversal

Understanding the impact of threshold voltage on MLC flash memory performance and reliability

Improving performance by matching imbalanced workloads with heterogeneous platforms

A programming system for xeon phis with runtime SIMD parallelization

Verifying micro-architecture simulators using event traces

Scalable analysis of multicore data reuse and sharing

HOMR: a hybrid approach to exploit maximum overlapping in MapReduce over high performance interconnects

Multi-stage coordinated prefetching for present-day processors

Load balancing n-body simulations with highly non-uniform density

Scalable performance analysis of exascale MPI programs through signature-based clustering algorithms

Accelerating cache coherence mechanism with speculation

DWC: dynamic write consolidation for phase change memory systems

Long-term resource fairness: towards economic fairness on pay-as-you-use computing systems

Unified on-chip memory allocation for SIMT architecture

Reducing energy consumption of NoC by router bypassing

Hardware-assisted scalable flow control of shared receive queue

Automating and optimizing data transfers for many-core coprocessors

Parallelizing and optimizing sparse tensor computations

Block value based insertion policy for high performance last-level caches

Content Provider	ACM Digital Library
Author	Cheng, Xu Li, Lingda Lu, Junlin
Abstract	Last-level cache performance has been proved to be crucial to the system performance. Essentially, any cache management policy improves performance by retaining blocks that it believes to have higher values preferentially. Most cache management policies use the access time or reuse distance of a block as its value to minimize total miss count. However, cache miss penalty is variable in modern systems due to i) variable memory access latency and ii) the disparity in latency toleration ability across different misses. Some recently proposed policies thus take into account the miss penalty as the block value. However, only considering miss penalty is not enough. In fact, the value of a block includes not only the penalty on its misses, but also the reduction of processor stall cycles on its hits, i.e., hit benefit. Therefore, we propose a method to compute both miss penalty and hit benefit. Then, the value of a block is calculated by accumulating all the miss penalty and hit benefits of its requests. Using our notion of block value, we propose Value based Insertion Policy (VIP) which aims to reserve more blocks with higher values in the cache. VIP keeps track of a small number of incoming and victim block pairs to learn the relationship between the value of the incoming block and that of the victim. On a miss, if the value of the incoming block is learned to be lower than that of the victim block in the past, VIP will predict that the incoming block is valueless and insert it with a high eviction priority. The evaluation shows that VIP can improve cache performance significantly in both single-core and multi-core environment while requiring a low storage overhead.
Starting Page	63
Ending Page	72
Page Count	10
File Format	PDF
ISBN	9781450326421
DOI	10.1145/2597652.2597653
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-06-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Last-level cache Insertion Value Hit benefit Miss penalty
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Bypass and insertion algorithms for exclusive last-level caches

Bypass and insertion algorithms for exclusive last-level caches

Bypass and insertion algorithms for exclusive last-level caches

Optimal bypass monitor for high performance last-level caches

Towards hybrid last level caches for chip-multiprocessors abstract — as cmp platforms are widely adopted.

Exploiting Spatial Locality in Data Caches using Spatial Footprints (1998)

Sampling Dead Block Prediction for Last-Level Caches

Adaptive insertion policies for high performance caching (2007)

Quantitative comparison of set-associative and victim caches.

Block value based insertion policy for high performance last-level caches

Similar Documents

Bypass and insertion algorithms for exclusive last-level caches

Bypass and insertion algorithms for exclusive last-level caches

Bypass and insertion algorithms for exclusive last-level caches

Optimal bypass monitor for high performance last-level caches

Towards hybrid last level caches for chip-multiprocessors abstract — as cmp platforms are widely adopted.

Exploiting Spatial Locality in Data Caches using Spatial Footprints (1998)

Sampling Dead Block Prediction for Last-Level Caches

Adaptive insertion policies for high performance caching (2007)

Quantitative comparison of set-associative and victim caches.

Block value based insertion policy for high performance last-level caches