NDLI: Cache Refill/Access Decoupling for Vector Machines

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Cache Refill/Access Decoupling for Vector Machines

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Cache Refill/Access Decoupling for Vector Machines

Content Provider	ACM Digital Library
Author	Asanovic, Krste Gerding, Steve Krashinsky, Ronny Batten, Christopher
Abstract	Vector processors often use a cache to exploit temporal locality and reduce memory bandwidth demands, but then require expensive logic to track large numbers of outstanding cache misses to sustain peak bandwidth from memory. We present refill/access decoupling, which augments the vector processor with a Vector Refill Unit (VRU) to quickly pre-execute vector memory commands and issue any needed cache line refills ahead of regular execution. The VRU reduces costs by eliminating much of the outstanding miss state required in traditional vector architectures and by using the cache itself as a cost-effective prefetch buffer. We also introduce vector segment accesses, a new class of vector memory instructions that efficiently encode two-dimensional access patterns. Segments reduce address bandwidth demands and enable more efficient refill/access decoupling by increasing the information contained in each vector memory command. Our results show that refill/access decoupling is able to achieve better performance with less resources than more traditional decoupling methods. Even with a small cache and memory latencies as long as 800 cycles, refill/access decoupling can sustain several kilobytes of in-flight data with minimal access management state and no need for expensive reserved element buffering.
Starting Page	331
Ending Page	342
Page Count	12
File Format	PDF
ISBN	0769521266
ISSN	10724451
DOI	10.1109/MICRO.2004.9
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-12-04
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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