NDLI: Fetching instruction streams

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Cherry: checkpointed early resource recycling in out-of-order microprocessors

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Fetching instruction streams

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Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

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Fetching instruction streams

Content Provider	ACM Digital Library
Author	Santana, Oliverio J. Ramirez, Alex Valero, Mateo Larriba-Pey, Josep L.
Abstract	Fetch performance is a very important factor because it effectively limits the overall processor performance. However, there is little performance advantage in increasing front-end performance beyond what the back-end can consume. For each processor design, the target is to build the best possible fetch engine for the required performance level A fetch engine will be better if it provides better performance, but also if it takes fewer resources, requires less chip area, or consumes less power.In this paper we propose a novel fetch architecture based on the execution of long streams of sequential instructions, taking maximum advantage of code layout optimizations. We describe our architecture in detail, and show that it requires less complexity and resources than other high performance fetch architectures like the trace cache, while providing a high fetch performance suitable for wide-issue super-scalar processors.Our results show that using our fetch architecture and code layout optimizations obtains 10% higher performance than the EV8 fetch architecture, and 4% higher than the FTB architecture using state-of-the-art branch predictors, while being only 1.5% slower than the trace cache. Even in the absence of code layout optimizations, fetching instruction streams is still 10% faster than the EV8, and only 4% slower than the trace cache.Fetching instruction streams effectively exploits the special characteristics of layout optimized codes to provide a high fetch performance, close to that of a trace cache, but has a much lower cost and complexity, similar to that of a basic block architecture.
Starting Page	371
Ending Page	382
Page Count	12
File Format	PDF
ISBN	0769518591
ISSN	10724451
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-11-18
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Fetching instruction streams

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Instruction fetching: coping with code bloat

Instruction Fetching Mechanisms for Superscalar Microprocessors (1996)

Modeled and measured instruction fetching performance for superscalar microprocessors (1998)

Instruction fetching mechanisms for superscalar microprocessors (1996)

Instruction fetching, scheduling, and forwarding in a dynamic multithreaded processor (2006).

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Modeled and measured instruction fetching performance for superscalar microprocessors (1998)

Fetching instruction streams

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Fetching instruction streams

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