NDLI: Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Please wait, while we are loading the content...

Cherry: checkpointed early resource recycling in out-of-order microprocessors

Instruction fetch deferral using static slack

Reduced code size modulo scheduling in the absence of hardware support

Three-dimensional memory vectorization for high bandwidth media memory systems

Generating physical addresses directly for saving instruction TLB energy

Vacuum packing: extracting hardware-detected program phases for post-link optimization

Microarchitectural exploration with Liberty

Managing static leakage energy in microprocessor functional units

Fetching instruction streams

Microarchitectural denial of service: insuring microarchitectural fairness

Characterizing and predicting value degree of use

Pointer cache assisted prefetching

Convergent scheduling

Dynamic addressing memory arrays with physical locality

Energy efficient frequent value data cache design

A faster optimal register allocator

Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

Optimizing pipelines for power and performance

Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors

Compiling for instruction cache performance on a multithreaded architecture

Hierarchical Scheduling Windows

Microarchitectural support for precomputation microthreads

Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

Reducing register ports for higher speed and lower energy

Compiler-directed instruction cache leakage optimization

DELI: a new run-time control point

Orion: a power-performance simulator for interconnection networks

Power protocol: reducing power dissipation on off-chip data buses

Exploiting data-width locality to increase superscalar execution bandwidth

A quantitative framework for automated pre-execution thread selection

Three extensions to register integration

Master/slave speculative parallelization

Compiler managed micro-cache bypassing for high performance EPIC processors

Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

Using modern graphics architectures for general-purpose computing: a framework and analysis

Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Content Provider	ACM Digital Library
Author	Semeraro, Greg Dropsho, Steven G. Magklis, Grigorios Dwarkadas, Sandhya Albonesi, David H. Scott, Michael L.
Abstract	We describe the design, analysis, and performance of an on--line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MCD microarchitecture allows the frequency/voltage of microprocessor regions to be adjusted independently and dynamically, allowing energy savings when the frequency of some regions can be reduced without significantly impacting performance.Our algorithm achieves on average a 19.0% reduction in Energy Per Instruction (EPI), a 3.2% increase in Cycles Per Instruction (CPI), a 16.7% improvement in Energy--Delay Product, and a Power Savings to Performance Degradation ratio of 4.6. Traditional frequency/voltage scaling techniques which apply reductions globally to a fully synchronous processor achieve a Power Savings to Performance Degradation ratio of only 2--3. Our Energy--Delay Product improvement is 85.5% of what has been achieved using an off--line algorithm. These results were achieved using a broad range of applications from the MediaBench, Olden, and Spec2000 benchmark suites using an algorithm we show to require minimal hardware resources.
Starting Page	356
Ending Page	367
Page Count	12
File Format	PDF
ISBN	0769518591
ISSN	10724451
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-11-18
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Dynamic frequency and voltage control for a multiple clock domain microarchitecture (2002)

Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture

Dynamic frequency and voltage control for a multiple clock domain microarchitecture (2002)

Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture (2002)

Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor (2003).

Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Similar Documents

Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Dynamic frequency and voltage control for a multiple clock domain microarchitecture (2002)

Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture

Dynamic frequency and voltage control for a multiple clock domain microarchitecture (2002)

Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture (2002)

Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor (2003).

Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Dynamic frequency and voltage control for a multiple clock domain microarchitecture