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Instruction Fetching Mechanisms for Superscalar Microprocessors (1996)
| Content Provider | CiteSeerX |
|---|---|
| Author | Wallace, Steven Bagherzadeh, Nader |
| Description | Instruction fetching is critical to the performance of a superscalar microprocessor. We develop a mathematical model for three different cache techniques and evaluate its performance both in theory and in simulation using the SPEC95 suite of benchmarks. In all the techniques, the fetching performance is dramatically lower than ideal expectations. To help remedy the situation, we also evaluate its performance using prefetching. Nevertheless, fetching performance is fundamentally limited by control transfers. To solve this problem, we introduce a new fetching mechanism called a dual branch target buffer. The dual branch target buffer enables fetching performance to leap beyond the limitation imposed by conventional methods and achieve a high instruction fetching rate. |
| File Format | |
| Language | English |
| Publisher Date | 1996-01-01 |
| Publisher Institution | In Proceedings of EURO-PAR'96 |
| Access Restriction | Open |
| Subject Keyword | Different Cache Technique High Instruction Instruction Fetching Conventional Method Spec95 Suite New Fetching Mechanism Ideal Expectation Fetching Performance Control Transfer Superscalar Microprocessor Dual Branch Target Buffer Mathematical Model |
| Content Type | Text |
| Resource Type | Article |
