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Balanced Prefetching Aggressiveness Controller for NoC-based Multiprocessor

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Balanced Prefetching Aggressiveness Controller for NoC-based Multiprocessor

Content Provider	ACM Digital Library
Author	Cireno, Maria Aziz, André Prado, Bruno Barros, Edna
Abstract	The performance gap between memory hierarchy and processor is a well-known issue and the prefetching approach is often used to minimize this problem. This technique performs a data prefetch in memory and makes it available in the private cache before its request. Thus, as more prefetching transactions are performed (very aggressive prefetching aggressiveness), the miss rate in the first levels of cache tends to be lower. However, a very aggressive prefetching can cause cache pollution, increase network traffic, and thereby degrade the system performance. In a multiprocessors platform, the prefetching of a core could interfere on the operation of others cores since they share resources, such as memory and network bandwidth. A very aggressive prefetching of a core can overload the network connection, increasing the communication which delays the network requests, increasing the penalty in the processor. In this context, this paper presents a Balanced Prefetching Aggressiveness Controller for a multiprocessor platform that minimizes the processor penalty. We tested the proposed controller in a network-based multiprocessor based on the Sparc V8. The results show a reduction of up to 23% and 7% on average in the processor's penalty, 34% in the cache pollution on average, and increase of 30% on prefetching accuracy for concurrent applications when compared to a system with fixed prefetching aggressiveness approach.
Starting Page	1
Ending Page	7
Page Count	7
File Format	PDF
ISBN	9781450331562
DOI	10.1145/2660540.2660541
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-09-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Cache coherence Multiprocessor Prefetching Network-on-chip Aggressiveness
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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