NDLI: Sharer status-based caching in tiled multiprocessor systems-on-chip

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Sharer status-based caching in tiled multiprocessor systems-on-chip

Content Provider	ACM Digital Library
Author	Zaib, A. Herkersdorf, A. Wallentowitz, S. Damodaran, P. Parayil Mana Wild, T.
Abstract	In multi-core systems with cache-to-cache forwarding, the data access latency depends heavily on the sharer status of cache-lines (CLs). The sharer status of a CL is defined by the number of copies of the CL in the whole system. Exclusive single-copy CLs have higher latency for different cache operations (e.g. misses, eviction, invalidation) when compared to shared multi-copy CLs. This is because, single-copy CL misses have to target globally shared system memory in case of a miss, while multi-copy misses may retrieve data from a CL in the neighborhood. These differences leads to dissimilarity in cache design requirements for single-copy CLs and multi-copy CLs. Unfortunately, state-of-the-art private cache designs do not consider this dissimilarity of CLs in all aspects of the cache design. This results in overhead in data access time and cache usage. In this paper, we present a concept of dynamic partitioning of the CLs depending on their sharer status (either single-copy or multi-copy). Based on this concept, we introduce a cache hierarchy in which the hierarchy levels are made different depending on the sharer status of CLs and vary dynamically according to application requirements. In addition, we propose an optimized coherence scheme that reduces the latency overhead of single-copy CLs. The scheme also provides an automatic write-upgrade which reduces the write access time. A cycle-accurate SystemC model of the proposed caching concept is simulated using SPLASH-2 and PARSEC benchmarks. It shows a more than 10% reduction in average memory access time compared to locality-aware adaptive cache models. It also shows a more than 40% reduction in average memory access time compared to cooperative cache models such as elastic and distributed cooperative caches where, these access latency benefits come at a cost of an on average 30% increase in network-on-chip (NoC) traffic. This once more underpins that an appropriately dimensioned on-chip interconnect is prerequisite for attaining high compute performance in large multi-core systems.
Starting Page	67
Ending Page	74
Page Count	8
File Format	PDF
ISBN	9781510801011
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-04-12
Publisher Place	San Diego
Access Restriction	Subscribed
Subject Keyword	Multiprocessor systems-on-chip Distributed directory cache coherence Cache partitioning Cache hierarchy
Content Type	Text
Resource Type	Article

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