NDLI: Synchronous sequential computation with molecular reactions

Please wait, while we are loading the content...

Application and realization of gateways between conventional automotive and IP/ethernet-based networks

MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems

Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification

To DFM or not to DFM?

Dimetrodon: processor-level preventive thermal management via idle cycle injection

Joint DAC/IWBDA special session design and synthesis of biological circuits

Modeling adaptive streaming applications with parameterized polyhedral process networks

Simultaneous functional and timing ECO

An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

Design, CAD and technology challenges for future processors: 3D perspectives

Test-case generation for embedded simulink via formal concept analysis

CIRUS: a scalable modular architecture for reusable drivers

Physics-based field-theoretic design automation tools for social networks and web search

MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs

Complexity and the challenges of securing SoCs

A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation

On the quantification of sustainability and extensibility of FlexRay schedules

TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead

Leakage-aware redundancy for reliable sub-threshold memories

Lithography at 14nm and beyond: choices and challenges

Cool shapers: shaping real-time tasks for improved thermal guarantees

Abstraction-based performance verification of NoCs

Distributed Resonant clOCK grid Synthesis (ROCKS)

A stabilized discrete empirical interpolation method for model reduction of electrical, thermal, and microelectromechanical systems

Transaction based pre-to-post silicon validation

Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system

Implicit permutation enumeration networks and binary decision diagrams reordering

Layout effects in fine grain 3D integrated regular microprocessor blocks

Efficient incremental analysis of on-chip power grid via sparse approximation

Single-molecule electronic detection using nanoscale field-effect devices

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores

Reliability analysis and improvement for multi-level non-volatile memories with soft information

A fast approach for static timing analysis covering all PVT corners

A fast solver for nonlocal electrostatic theory in biomolecular science and engineering

MO-pack: many-objective clustering for FPGA CAD

Facing the challenge of new design features: an effective verification approach

CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations

Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language

DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips

Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems

A closed-form expression for estimating minimum operating voltage $(V_{DDmin})$ of CMOS logic gates

EFFEX: an embedded processor for computer vision based feature extraction

Challenges in a future IP/ethernet-based in-car network for real-time applications

Plugging versus logging: a new approach to write buffer management for solid-state disks

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs

Self-aligned double patterning decomposition for overlay minimization and hot spot detection

Dynamic thermal management for multimedia applications using machine learning

Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming

Interpolation-based incremental ECO synthesis for multi-error logic rectification

Gridless pin access in detailed routing

Hybrid modeling of non-stationary process variations

3D heterogeneous system integration: application driver for 3D technology development

A first step towards automatic application of power analysis countermeasures

Programming challenges & solutions for multi-processor SoCs: an industrial perspective

Can we go towards true 3-D architectures?

Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials

High-performance energy-efficient encryption in the sub-45nm CMOS Era

Simulation environment configuration for parallel simulation of multicore embedded systems

Generalized reliability-oriented energy management for real-time embedded applications

Testability driven statistical path selection

A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library

New sub-20nm transistors: why and how

ChronOS Linux: a best-effort real-time multiprocessor Linux kernel

Global convergence analysis of mixed-signal systems

WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing

A novel framework for passive macro-modeling

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

An algorithm-architecture co-design framework for gridding reconstruction using FPGAs

Using SAT-based Craig interpolation to enlarge clock gating functions

Fault-tolerant 3D clock network

Power grid verification using node and branch dominance

CMOS compatible nanowires for biosensing

Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance

Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

Biochemical oscillator sensitivity analysis in the presence of conservation constraints

Enforcing architectural contracts in high-level synthesis

Learning microarchitectural behaviors to improve stimuli generation quality

A case for NEMS-based functional-unit power gating of low-power embedded microprocessors

Process-level virtualization for runtime adaptation of embedded software

A fault-tolerant NoC scheme using bidirectional channel

A helper thread based dynamic cache partitioning scheme for multithreaded applications

Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding

Rigorous model-based design & verification flow for in-vehicle software

A version-based strategy for reliability enhancement of flash file systems

Dynamic voltage scaling of OLED displays

Statistical characterization of standard cells using design of experiments with response surface modeling

Improved post-silicon power modeling using AC lock-in techniques

CuMAPz: a tool to analyze memory access patterns in CUDA

Optimal multi-domain clock skew scheduling

An optimal algorithm for layer assignment of bus escape routing on PCBs

Efficient SRAM failure rate prediction via Gibbs sampling

3D integration for energy efficient system design

TPM-SIM: a framework for performance evaluation of trusted platform modules

Thermal-aware system analysis and software synthesis for embedded multi-processors

Orchestrated multi-level information flow analysis to understand SoCs

Automatic stability checking for large linear analog integrated circuits

The state-of-the-art in semiconductor reverse engineering

Transaction level statistical analysis for efficient micro-architectural power and performance studies

Customer-aware task allocation and scheduling for multi-mode MPSoCs

Diagnosing scan clock delay faults through statistical timing pruning

Layout aware line-edge roughness modeling and poly optimization for leakage minimization

Circuit design challenges at the 14nm technology node

Efficient WCRT analysis of synchronous programs using reachability

Litmus tests for comparing memory consistency models: how long do they need to be?

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits

A highly scalable parallel boundary element method for capacitance extraction

A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation

A low-energy computation platform for data-driven biomedical monitoring algorithms

Power reduction via separate synthesis and physical libraries

An integrated algorithm for 3D-IC TSV assignment

Power grid correction using sensitivity analysis under an RC model

Heterogeneous integration of carbon nanotubes and graphene microassemblies for environmental and breath sensing

Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips

High effective-resolution built-in jitter characterization with quantization noise shaping

Flexible 2D layout decomposition framework for spacer-type double pattering lithography

In silico synchronization of cellular populations through expression data deconvolution

Shared reconfigurable fabric for multi-core customization

Robust partitioning for hardware-accelerated functional verification

Automated mapping for reconfigurable single-electron transistor arrays

Virtualizing embedded systems: why bother?

Process variation-aware routing in NoC based multicores

A reuse-aware prefetching scheme for scratchpad memory

Fast algorithms for IR voltage drop analysis exploiting locality

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study

Understanding the impact of power loss on flash memory

Power management of hybrid DRAM/PRAM-based main memory

Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries

Thermal signature: a simple yet accurate thermal index for floorplan optimization

SEAL: soft error aware low power scheduling by Monte Carlo state space under the influence of stochastic spatial and temporal dependencies

Re-synthesis for cost-efficient circuit-level timing speculation

A distributed algorithm for layout geometry operations

Direct matrix solution of linear complexity for surface integral-equation based impedance extraction of high bandwidth interconnects

Applications driving 3D integration and corresponding manufacturing challenges

Differential public physically unclonable functions: architecture and applications

Temporal isolation on multiprocessing architectures

Dynamic binary translation to a reconfigurable target for on-the-fly acceleration

Performance bound analysis of analog circuits considering process variations

Extracting behavior and dynamically generated hierarchy from SystemC models

Symbolic system synthesis in the presence of stringent real-time constraints

Diagnosis of transition fault clusters

Post sign-off leakage power optimization

Fast and accurate source-level simulation of software timing considering complex code optimizations

Formal hardware/software co-verification by interval property checking with abstraction

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Fast multipole method on GPU: tackling 3-D capacitance extraction on massively parallel SIMD platforms

Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks

Are logic synthesis tools robust?

Non-uniform micro-channel design for stacked 3D-ICs

Design sensitivity of single event transients in scaled logic circuits

Design of robust metabolic pathways

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection

Synchronous sequential computation with molecular reactions

Threadmill: a post-silicon exerciser for multi-threaded processors

Universal logic modules based on double-gate carbon nanotube transistors

Virtualizing real-time embedded systems with Java

Enabling system-level modeling of variation-induced faults in networks-on-chips

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms

Decoupling for power gating: sources of power noise and design strategies

RJOP: a customized Java processor for reactive embedded systems

Integrated circuit security techniques using variable supply voltage

Device aging-based physically unclonable functions

Rethinking memory redundancy: optimal bit cell repair for maximum-information storage

Throughput maximization for periodic real-time systems under the maximal temperature constraint

Supervised design space exploration by compositional approximation of Pareto sets

Dynamic effort scaling: managing the quality-efficiency tradeoff

TSV-aware analytical placement for 3D IC designs

Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors

FlexiBuffer: reducing leakage power in on-chip network routers

Wear rate leveling: lifetime enhancement of PRAM with endurance variation

Error-resilient low-power DSP via path-delay shaping

Hermes: an integrated CPU/GPU microarchitecture for IP routing

Information flow isolation in I2C and USB

Significance driven computation on next-generation unreliable platforms

Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability

Performance optimization of error detection based on speculative reconfiguration

Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory

Emulation based high-accuracy throughput estimation for high-speed connectivities: case study of USB2.0

Thermal-aware cell and through-silicon-via co-placement for 3D ICs

In-field aging measurement and calibration for power-performance optimization

Capacity optimized NoC for multi-mode SoC

Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

MARSS: a full system simulator for multicore x86 CPUs

Synchronous sequential computation with molecular reactions

Content Provider	ACM Digital Library
Author	Parhi, Keshab Riedel, Marc Jiang, Hua
Abstract	Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit volume). Prior work has established mechanisms for implementing logical and arithmetic functions including addition, multiplication, exponentiation, and logarithms with molecular reactions. In this paper, we present a general methodology for implementing synchronous sequential computation. We generate a four-phase clock signal through robust, sustained chemical oscillations. We implement memory elements by transferring concentrations between molecular types in alternating phases of the clock. We illustrate our design methodology with examples: a binary counter as well as a four-point, two-parallel FFT. We validate our designs through ODE simulations of mass-action chemical kinetics. We are exploring DNA-based computation via strand displacement as a possible experimental chassis.
Starting Page	836
Ending Page	841
Page Count	6
File Format	PDF
ISBN	9781450306362
ISSN	85644924
DOI	10.1145/2024724.2024911
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-06-05
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Synchronous logic Digital design Sequential logic Synthetic biology Computational biology Molecular computation
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in