NDLI: Post sign-off leakage power optimization

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Post sign-off leakage power optimization

Content Provider	ACM Digital Library
Author	Abrishami, Hamed Pedram, Massoud Qin, Jeff Froessl, Juergen Lou, Jinan
Abstract	With the scaling down of the CMOS technologies, leakage power is becoming an increasingly important issue in IC design. There is a trade-off between subthreshold leakage power consumption and clock frequency in the circuit; i.e., for higher performance, leakage power consumption must be sacrificed and vice versa. Meanwhile, timing analysis during synthesis and physical design is pessimistic, which means there are some slacks available to be traded for leakage power minimization. This power minimization can be done after the sign-off which is more accurate and realistic than if it is done before the sign-off. The available slack can be traded for leakage power minimization by footprint-based cell swapping and threshold voltage assignment. In this paper, we introduce our post sign-off leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We set up a novel transformation technique to manipulate the constraints of the optimization problem to be solved by CG. We show that by doing this optimization we can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off. All experiments are done on the real industrial designs.
Starting Page	453
Ending Page	458
Page Count	6
File Format	PDF
ISBN	9781450306362
ISSN	85644924
DOI	10.1145/2024724.2024829
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-06-05
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Slack Path-based analysis Sign-off Conjugate gradient Leakage power Optimization
Content Type	Text
Resource Type	Article

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