NDLI: Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding

Please wait, while we are loading the content...

Big Data Analytics on Flash Storage with Accelerators

Combating the Reliability Challenge of GPU Register File at Low Supply Voltage

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding

Accelerating Linked-list Traversal Through Near-Data Processing

Greater Performance and Better Efficiency: Predicated Execution has shown us the way

WearCore: A Core for Wearable Workloads

Speculatively Exploiting Cross-Invocation Parallelism

Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models

Characterizing and Optimizing the Performance of Multithreaded Programs Under Interference

Scaling Data Analytics with Moore's Law

Bridging the Semantic Gaps of GPU Acceleration for Scale-out CNN-based Big Data Processing: Think Big, See Small

Vectorization of Multibyte Floating Point Data Formats

POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism For Energy-Efficient Networks-on-Chip

Student Research Poster: Slack-Aware Shared Bandwidth Management in GPUs

μC-States: Fine-grained GPU Datapath Power Management

Fusion of Parallel Array Operations

Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management

Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs

MicroSpec: Speculation-Centric Fine-Grained Parallelization for FSM Computations

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

Optimizing Indirect Memory References with milk

A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs

Rinnegan: Efficient Resource Use in Heterogeneous Architectures

POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware

Student Research Poster: From Processing-in-Memory to Processing-in-Storage

Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities

Reduction Drawing: Language Constructs and Polyhedral Compilation for Reductions on GPU

A Static Cut-off for Task Parallel Programs

Power Tuning HPC Jobs on Power-Constrained Systems

Hash Map Inlining

Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs

Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading

POSTER: Easy PRAM-based High-Performance Parallel Programming with ICE

Student Research Poster: Network Controller Emulation on a Sidecore for Unmodified Virtual Machines

OAWS: Memory Occlusion Aware Warp Scheduling

Resource Conscious Reuse-Driven Tiling for GPUs

Online Scalability Characterization of Data-Parallel Programs on Many Cores

Sparso: Context-driven Optimizations of Sparse Linear Algebra

CAF: Core to Core Communication Acceleration Framework

EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions

POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support

Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness

POSTER: Collective Dynamic Parallelism for Directive Based GPU Programming Languages and Compilers

Student Research Poster: A Scalable General Purpose System for Large-Scale Graph Processing

POSTER: Firestorm: Operating Systems for Power-Constrained Architectures

Student Research Poster: Compiling Boolean Circuits to Non-deterministic Branching Programs to be Implemented by Light Switching Circuits.

POSTER: ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies

Student Research Poster: Software Out-of-Order Execution for In-Order Architectures

POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics

POSTER: SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization

POSTER: Hybrid Data Dependence Analysis for Loop Transformations

POSTER: An Optimization of Dataflow Architectures for Scientific Applications

POSTER: hVISC: A Portable Abstraction for Heterogeneous Parallel Systems

POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core

POSTER: Pagoda: A Runtime System to Maximize GPU Utilization in Data Parallel Tasks with Limited Parallelism

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding

Content Provider	ACM Digital Library
Author	Kelly, Paul H.J. Kotselidis, Christos Bodin, Bruno Mawer, John Franke, Björn Emani, Murali Zia, M. Zeeshan Lujan, Mikel Nardi, Luigi Nisbet, Andy O'Boyle, Michael Sreekar Shenoy, Govind Wagstaff, Harry
Abstract	System designers typically use well-studied benchmarks to evaluate and improve new architectures and compilers. We design tomorrow's systems based on yesterday's applications. In this paper we investigate an emerging application, 3D scene understanding, likely to be significant in the mobile space in the near future. Until now, this application could only run in real-time on desktop GPUs. In this work, we examine how it can be mapped to power constrained embedded systems. Key to our approach is the idea of incremental co-design exploration, where optimization choices that concern the domain layer are incrementally explored together with low-level compiler and architecture choices. The goal of this exploration is to reduce execution time while minimizing power and meeting our quality of result objective. As the design space is too large to exhaustively evaluate, we use active learning based on a random forest predictor to find good designs. We show that our approach can, for the first time, achieve dense 3D mapping and tracking in the real-time range within a 1W power budget on a popular embedded device. This is a 4.8x execution time improvement and a 2.8x power reduction compared to the state-of-the-art.
Starting Page	57
Ending Page	69
Page Count	13
File Format	PDF
ISBN	9781450341219
DOI	10.1145/2967938.2967963
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-09-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Computer vision Embedded systems Slam Dse Design space exploration
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in