NDLI: Tradeoffs in instruction format design for horizontal architectures

Content Provider	ACM Digital Library
Author	Sohi, Gurindar S. Vajapeyam, Sriram
Abstract	With recent improvements in software techniques and the enhanced level of fine grain parallelism made available by such techniques, there has been an increased interest in horizontal architectures and large instruction words that are capable of issuing more that one operation per instruction. This paper investigates some issues in the design of such instruction formats. We study how the choice of an instruction format is influenced by factors such as the degree of pipelining and the instruction's view of the register file. Our results suggest that very large instruction words capable of issuing one operation to each functional unit resource in a horizontal architecture may be overkill. Restricted instruction formats with limited operation issuing capabilities are capable of providing similar performance (measured by the total number of time steps) with significantly less hardware in many cases.
Starting Page	15
Ending Page	25
Page Count	11
File Format	PDF
ISBN	0897913000
DOI	10.1145/70082.68184
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1989-04-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Tradeoffs in instruction format design for horizontal architectures