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Tradeoffs in Arithmetic Architectures for Cordic Algorithm Design
| Content Provider | Semantic Scholar |
|---|---|
| Author | Giacomantone, Javier |
| Copyright Year | 2001 |
| Abstract | The COordinate Rotational DIgital Computer (CORDIC) is an arithmetic algorithm widely used in the computing of elementary functions and digital signal processing applications, particularly where large amounts of rotation operations are necessary. After a survey of the principal architectures for the design of a CORDIC processor, a pipeline scheme is presented to achieve performance enhancement at an architectural level. Circuit complexity constrains and performance limits for each option are provided. The design is geared to programmable devices but the architectural level design and the analysis of constrains are independent of the specific target. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://iie.fing.edu.uy/vlsi/iberchip/pdf/30.pdf |
| Alternate Webpage(s) | http://iie.fing.edu.uy/investigacion/grupos/microele//iberchip/pdf/30.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
