NDLI: Data buffering: run-time versus compile-time support

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Data buffering: run-time versus compile-time support

Content Provider	ACM Digital Library
Author	Mulder, H.
Abstract	Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion.
Starting Page	144
Ending Page	151
Page Count	8
File Format	PDF
ISBN	0897913000
DOI	10.1145/70082.68196
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1989-04-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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