NDLI: A compile-time managed multi-level register file hierarchy

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A compile-time managed multi-level register file hierarchy

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A compile-time managed multi-level register file hierarchy

Content Provider	ACM Digital Library
Author	Gebhart, Mark Keckler, Stephen W. Dally, William J.
Abstract	As processors increasingly become power limited, performance improvements will be achieved by rearchitecting systems with energy efficiency as the primary design constraint. While some of these optimizations will be hardware based, combined hardware and software techniques likely will be the most productive. This work redesigns the register file system of a modern throughput processor with a combined hardware and software solution that reduces register file energy without harming system performance. Throughput processors utilize a large number of threads to tolerate latency, requiring a large, energy-intensive register file to store thread context. Our results show that a compiler controlled register file hierarchy can reduce register file energy by up to 54%, compared to a hardware only caching approach that reduces register file energy by 34%. We explore register allocation algorithms that are specifically targeted to improve energy efficiency by sharing temporary register file resources across concurrently running threads and conduct a detailed limit study on the further potential to optimize operand delivery for throughput processors. Our efficiency gains represent a direct performance gain for power limited systems, such as GPUs.
Starting Page	465
Ending Page	476
Page Count	12
File Format	PDF
ISBN	9781450310536
DOI	10.1145/2155620.2155675
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-12-03
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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