NDLI: And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

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And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

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And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

Content Provider	ACM Digital Library
Author	Shukla, Sunil Bacon, David F. Cheng, Perry
Abstract	Programmers are turning to radical architectures such as reconfigurable hardware (FPGAs) to achieve performance. But such systems, programmed at a very low level in languages with impoverished abstractions, are orders of magnitude more complex to use than conventional CPUs. The continued exponential increase in transistors, combined with the desire to implement ever more sophisticated algorithms, makes it imperative that such systems be programmed at much higher levels of abstraction. One of the fundamental high-level language features is automatic memory management in the form of garbage collection. We present the first implementation of a complete garbage collector in hardware (as opposed to previous "hardware-assist" techniques), using an FPGA and its on-chip memory. Using a completely concurrent snapshot algorithm, it provides single-cycle access to the heap, and never stalls the mutator for even a single cycle, achieving a deterministic mutator utilization (MMU) of 100%. We have synthesized the collector to hardware and show that it never consumes more than 1% of the logic resources of a high-end FPGA. For comparison we also implemented explicit (malloc/free) memory management, and show that real-time collection is about 4% to 17% slower than malloc, with comparable energy consumption. Surprisingly, in hardware real-time collection is superior to stop-the-world collection on every performance axis, and even for stressful micro-benchmarks can achieve 100% MMU with heaps as small as 1.01 to 1.4 times the absolute minimum.
Starting Page	23
Ending Page	34
Page Count	12
File Format	PDF
ISBN	9781450312059
DOI	10.1145/2254064.2254068
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Block ram Garbage collection Fpga High level synthesis Real time
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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And then there were none:a stall-free real-time garbage collector for reconfigurable hardware

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And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

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