NDLI: A compiler framework for extracting superword level parallelism

Please wait, while we are loading the content...

Compiling a high-level language for GPUs: (via language support for architectures and compilers)

The implicit calculus: a new foundation for generic programming

Algorithmic profiling

Language-based control and mitigation of timing channels

Parcae: a system for flexible parallel execution

Proving acceptability properties of relaxed nondeterministic approximate programs

Sound and precise analysis of parallel programs through schedule specialization

Fast and precise hybrid type inference for JavaScript

Type-directed completion of partial expressions

Synchronising C/C++ and POWER

A compiler framework for extracting superword level parallelism

Verifying GPU kernels by test amplification

Concurrent data representation synthesis

A dynamic program analysis to find floating-point accuracy problems

Effective parallelization of loops in the presence of I/O operations

Fully automatic and precise detection of thread safety violations

Adaptive input-aware compilation for graphics engines

Deterministic parallelism via liquid effects

Understanding and detecting real-world performance bugs

Diderot: a parallel DSL for image analysis and visualization

JANUS: exploiting parallelism via hindsight

Automated error diagnosis using abductive inference

Parallelizing top-down interprocedural analyses

Race detection for web applications

Self-stabilizing Java

SuperC: parsing all of C by taming the preprocessor

Speculative separation for privatization and reductions

RockSalt: better, faster, stronger SFI for the x86

Dynamic synthesis for relaxed memory models

Chimera: hybrid program analysis for determinism

Polyhedra scanning revisited

Scalable and precise dynamic datarace detection for structured parallelism

And then there were none: a stall-free real-time garbage collector for reconfigurable hardware

Speculative linearizability

Input-sensitive profiling

Synthesising graphics card programs from DSLs

Reagents: expressing and composing fine-grained concurrency

Efficient state merging in symbolic execution

Design and implementation of sparse global analyses for C-like languages

Engage: a deployment management system

Type-directed automatic incrementalization

Test-case reduction for C compiler bugs

Dynamic trace-based analysis of vectorization potential of applications

Synthesizing software verifiers from proof rules

Automated synthesis of symbolic instruction encodings from I/O samples

Static analysis and compiler design for idempotent processing

Logical inference techniques for loop parallelization

Multicore acceleration of priority-based schedulers for concurrency bug detection

A compiler framework for extracting superword level parallelism

Content Provider	ACM Digital Library
Author	Zhang, Yuanrui Liu, Jun Ding, Wei Kandemir, Mahmut Jang, Ohyoung
Abstract	SIMD (single-instruction multiple-data) instruction set extensions are quite common today in both high performance and embedded microprocessors, and enable the exploitation of a specific type of data parallelism called SLP (Superword Level Parallelism). While prior research shows that significant performance savings are possible when SLP is exploited, placing SIMD instructions in an application code manually can be very difficult and error prone. In this paper, we propose a novel automated compiler framework for improving superword level parallelism exploitation. The key part of our framework consists of two stages: superword statement generation and data layout optimization. The first stage is our main contribution and has two phases, statement grouping and statement scheduling, of which the primary goals are to increase SIMD parallelism and, more importantly, capture more superword reuses among the superword statements through global data access and reuse pattern analysis. Further, as a complementary optimization, our data layout optimization organizes data in memory space such that the price of memory operations for SLP is minimized. The results from our compiler implementation and tests on two systems indicate performance improvements as high as 15.2% over a state-of-the-art SLP optimization algorithm.
Starting Page	347
Ending Page	358
Page Count	12
File Format	PDF
ISBN	9781450312059
DOI	10.1145/2254064.2254106
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Compiler Slp Data layout Scheduling Simd
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A compiler framework for extracting superword level parallelism

A New Algorithm to Exploit Superword Level Parallelism

DM-SIMD: A new SIMD predication mechanism for exploiting superword level parallelism

Exploiting Pure Superword Level Parallelism for Array Indirections

Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study (2007)

Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study (2007)

Exploiting Superword Level Parallelism with . . . (2000)

Compiler optimizations for architectures supporting superword-level parallelism

Exploiting mixed SIMD parallelism by reducing data reorganization overhead

A compiler framework for extracting superword level parallelism

Similar Documents

A compiler framework for extracting superword level parallelism

A New Algorithm to Exploit Superword Level Parallelism

DM-SIMD: A new SIMD predication mechanism for exploiting superword level parallelism

Exploiting Pure Superword Level Parallelism for Array Indirections

Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study (2007)

Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study (2007)

Exploiting Superword Level Parallelism with . . . (2000)

Compiler optimizations for architectures supporting superword-level parallelism

Exploiting mixed SIMD parallelism by reducing data reorganization overhead

A compiler framework for extracting superword level parallelism