NDLI: High-level power analysis for on-chip networks

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High-level power analysis for on-chip networks

Content Provider	ACM Digital Library
Author	Eisley, Noel Peh, Li-Shiuan
Abstract	As on-chip networks become prevalent in multiprocessor systems-on-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power increasingly the primary constraint in chips, the tool chain in systems design, from simulation infrastructures to compilers and synthesis frameworks, needs to take network power into account, motivating the need for early-stage communication power analysis.While there has been substantial research in network performance analysis that enabled critical insights into network design, no power analysis frameworks for networks exist. In this paper, we propose such a framework that takes as input message flows, and derives a power profile of the network fabric, capturing both the spatial variance across the network fabric as well as the temporal variance across application execution time. Our analysis is based on link utilization as the unit of abstraction for network power, with contention among message flows modeled through propagation of overflow areas in link utilization functions. When validated against Orion, a cycle-accurate network power simulator, we show that relative trends in network power are well-preserved. We then demonstrate potential uses of our analysis framework through three case studies, from speedup of multiprocessor and network simulations, to facilitating power-aware communication synthesis and compiler code placement.
Starting Page	104
Ending Page	115
Page Count	12
File Format	PDF
ISBN	1581138903
DOI	10.1145/1023833.1023849
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-09-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Systems-on-a-chip (soc) Simulation Link utilization Power analysis
Content Type	Text
Resource Type	Article

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