NDLI: Flip-flop insertion with shifted-phase clocks for FPGA power reduction

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Storage assignment during high-level synthesis for configurable architectures

Performance-driven read-after-write dependencies softening in high-level synthesis

An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications

FPGA device and architecture evaluation considering process variations

Via-configurable routing architectures and fast design mappability estimation for regular fabrics

SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill

Computational geometry based placement migration

An efficient and effective detailed placement algorithm

Post-placement rewiring and rebuffering by exhaustive search for functional symmetries

Wirelength optimization by optimal block orientation

Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions

Response shaper: a novel technique to enhance unknown tolerance for output response compaction

Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs

A cocktail approach on random access scan toward low power and high efficiency test

A statistical study of the effectiveness of BIST jitter measurement techniques

The circuit design of the synergistic processor element of a CELL processor

Adaptive designs for power and thermal optimization

Digital RF processor (DRP/spl trade/) for cellular phones

A layout dependent full-chip copper electroplating topography model

Interval-valued statistical modeling of oxide chemical-mechanical polishing

Fast and efficient phase conflict detection and correction in standard-cell layouts

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs

Robust mixed-size placement under tight white-space constraints

Intrinsic shortest path length: a new, accurate a priori wirelength estimator

Synthesis methodology for built-in at-speed testing

Clustering for processing rate optimization

ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing

FinFETs for nanoscale CMOS digital integrated circuits

Physics-based compact modeling for nonclassical CMOS

Double-gate SOI devices for low-power and high-performance applications

Thermal simulation techniques for nanoscale transistors

An automated technique for topology and route generation of application specific on-chip interconnection networks

Deadlock-free routing and component placement for irregular mesh-based networks-on-chip

Application-specific network-on-chip architecture customization via long-range link insertion

NoCEE: energy macro-model extraction methodology for network on chip routers

Architecture and compilation for data bandwidth improvement in configurable embedded processors

Code restructuring for improving cache performance of MPSoCs

2D data locality: definition, abstraction, and application

Integrating loop and data optimizations for locality within a constraint network based framework

System level verification of digital signal processing applications based on the polynomial abstraction technique

Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra

RTL SAT simplification by Boolean and interval arithmetic reasoning

Runtime integrity checking for inter-object connections

Post-placement voltage island generation under performance requirement

Buffer insertion under process variations for delay minimization

Efficient algorithms for buffer insertion in general circuits based on network flow

Trade-off between latch and flop for min-period sequential circuit designs with crosstalk

Flip-flop insertion with shifted-phase clocks for FPGA power reduction

Acyclic modeling of combinational loops

Fast algorithms for IR drop analysis in large power grid

Incremental partitioning-based vectorless power grid verification

Static timing analysis considering power supply variations

Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation

Performance analysis of carbon nanotube interconnects for VLSI applications

DiCER: distributed and cost-effective redundancy for variation tolerance

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Noise margin analysis for dynamic logic circuits

Efficient analog platform characterization through analog constraint graphs

Performance-centering optimization for system-level analog design exploration

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits

Battery optimization vs energy optimization: which to choose and when?

Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems

Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications

Compiler-directed voltage scaling on communication links for reducing power consumption

Design automation issues for biofluidic microchips

Design of DNA origami

Kauffman networks: analysis and applications

Parameterized model order reduction of nonlinear dynamical systems

Fast-yet-accurate PVT simulation by combined direct and iterative methods

Robust automated synthesis methodology for integrated spiral inductors with variability

Statistical technology mapping for parametric yield

Reducing structural bias in technology mapping

Improving the efficiency of static timing analysis with false paths

Total power-optimal pipelining and parallel processing under process variations in nanometer technology

Serial-link bus: a low-power on-chip bus architecture

New decompilation techniques for binary-level co-processor generation

Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays

Eliminating wire crossings for molecular quantum-dot cellular automata implementation

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

TACO: temperature aware clock-tree optimization

Statistical based link insertion for robust clock network design

Practical techniques to reduce skew and its variations in buffered clock networks

An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators

Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators

A multi-harmonic probe technique for computing oscillator steady states

An efficient and accurate algorithm for autonomous envelope following with applications

Steady-state analysis of voltage and current controlled oscillators

Timing-aware power noise reduction in layout

A high efficiency full-chip thermal simulation algorithm

Fast thermal simulation for architecture level dynamic thermal management

Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality

The impact of the nanoscale on computing systems

Computer-aided design for DNA self-assembly: process and applications

A mapping algorithm for defect-tolerance of reconfigurable nano-architectures

FastSies: a fast stochastic integral equation solver for modeling the rough surface effect

Efficient statistical capacitance variability modeling with orthogonal principle factor analysis

Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

Statistical critical path analysis considering correlations

Discrete Vt assignment and gate sizing using a self-snapping continuous formulation

Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs

Projection-based performance modeling for inter/intra-die variations

System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS)

Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

Thermal via planning for 3-D ICs

A routing algorithm for flip-chip design

An escape routing framework for dense boards with high-speed design constraints

Optimal routing algorithms for pin clusters in high-density multichip modules

Weighted control scheduling

Hardware synthesis from guarded atomic actions with performance specifications

Fast timing closure by interconnect criticality driven delay relaxation

Sesison 9B - Advances in model order reduction approaches

Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration

Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations

A more reliable reduction algorithm for behavioral model extraction

An efficient method for terminal reduction of interconnect circuits considering delay variations

Statistical timing analysis with two-sided constraints

A unified framework for statistical timing analysis with coupling and multiple input switching

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

Verification of executable pipelined machines with bit-level interfaces

A complete compositional reasoning framework for the efficient verification of pipelined machines

Post-verification debugging of hierarchical designs

Efficient LTL compilation for SAT-based model checking

SAT based solutions for consistency problems in formal property specifications for open systems

Architecture and details of a high quality, large-scale analytical placer

Mixed-size placement via line search

A hybrid linear equation solver and its application in quadratic placement

Energy-efficient platform designs for real-world wireless sensing applications

Power-aware microsensor design

System software techniques for low-power operation in wireless sensor networks

Expanding the frequency range of AWE via time shifting

A sliding window scheme for accurate clock mesh analysis

Accurate delay computation for noisy waveform shapes

Pessimism reduction in crosstalk noise aware STA

Embedded tutorial: formal equivalence checking between system-level models and RTL

CDMA/FDMA-interconnects for future ULSI communications

The feasibility of on-chip interconnection using antennas

Global signaling over lossy transmission lines

A cache-defect-aware code placement algorithm for improving the performance of processors

Improving scratch-pad memory reliability through compiler-guided data block duplication

An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems

Memory access optimization of dynamic binary translation for reconfigurable architectures

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

Gate sizing using incremental parameterized statistical timing analysis

Statistical gate sizing for timing yield optimization

Simulation-based bug trace minimization with BMC-based refinement

Complementary use of runtime validation and model checking

Scalable compositional minimization via static analysis

Transition-by-transition FSM traversal for reachability analysis in bounded model checking

Automatic generalized phase abstraction for formal verification

ICCAD-2005 International Conference on Computer Aided Design (IEEE Cat. No. 05CH37700)

Flip-flop insertion with shifted-phase clocks for FPGA power reduction

Content Provider	ACM Digital Library
Author	Cho, Youngjin Chang, Naehyuck Lim, Hyeonmin Lee, Kyungsoo
Abstract	Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops. This results in unwanted glitch propagation along the LUTs, and wastes power. This paper proposes a flip-flop insertion, we propose insertion of new flip-flops between adjacent existing flip-flops to minimize glitch propagation and power loss. Each new flip-flop is timed by a phase-shifted clock with the phase calculated from the delays of LUTs and routing paths. This is different from traditional retiming methods that use the original clock or an 180-degree clock for the new flip-flops, and thus alters the original pipeline structure and synchronization. We start from a post-layout design, retiming its clock frequency and timing behavior. Multiple flip-flop insertion is an NP-complete problem because each new flip-flop affects the delays in the design. We have devised a glitch generation and propagation model for LUT-based FPGAs that take account of path delays while supporting reasonable complexity. We propose effective heuristics for flip-flop insertion and clock phase selection. Full-chip measurements, including all the overheads associated with the inserted flip-flops, show that our approach shows up to 38% of the total dynamic power. We have analyzed our scheme, showing the mechanics of clock assignment and glitch minimization, and the sources of power reduction.
Starting Page	335
Ending Page	342
Page Count	8
File Format	PDF
ISBN	078039254X
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-05-31
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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