NDLI: Instruction cache locking inside a binary rewriter

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Instruction cache locking inside a binary rewriter

Content Provider	ACM Digital Library
Author	Barua, Rajeev Anand, Kapil
Abstract	Cache memories in embedded systems play an important role in reducing the execution time of the applications. Various kinds of extensions have been added to cache hardware to enable software involvement in replacement decisions, thus improving the run-time over a purely hardware-managed cache. Novel embedded systems, like Intel's Xscale and ARM Cortex processors provide the facility of locking one or more lines in cache - this feature is called cache locking. This paper presents the first method in the literature for instruction-cache locking that is able to reduce the average-case run-time of the program. We devise a cost-benefit model to discover the memory addresses which should be locked in the cache. We implement our scheme inside a binary rewriter, thus widening the applicability of our scheme to binaries compiled using any compiler. Results obtained on a suite of MiBench and MediaBench benchmarks show up to 25% improvement in the instruction-cache miss rate on average and up to 13.5% improvement in the execution time on average for applications having instruction accesses as a bottleneck, depending on the cache configuration. The improvement in execution time is as high as 23.5% for some benchmarks.
Starting Page	185
Ending Page	194
Page Count	10
File Format	PDF
ISBN	9781605586267
DOI	10.1145/1629395.1629422
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-10-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Binary rewriting Embedded systems Caches Cache locking
Content Type	Text
Resource Type	Article

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