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Instruction cache locking inside a binary rewriter (2009)
| Content Provider | CiteSeerX |
|---|---|
| Author | Anand, Kapil Barua, Rajeev |
| Description | Cache memories in embedded systems play an important role in reducing the execution time of the applications. Var-ious kinds of extensions have been added to cache hard-ware to enable software involvement in replacement deci-sions, thus improving the run-time over a purely hardware-managed cache. Novel embedded systems, like Intel’s Xscale and ARM Cortex processors provide the facility of locking one or more lines in cache- this feature is called cache lock-ing. This paper presents the first method in the literature for instruction-cache locking that is able to reduce the average-case run-time of the program. We devise a cost-benefit model to discover the memory addresses which should be locked in the cache. We implement our scheme inside a bi-nary rewriter, thus widening the applicability of our scheme to binaries compiled using any compiler. Results obtained on a suite of MiBench and MediaBench benchmarks show up to 25 % improvement in the instruction-cache miss rate on average and up to 13.5 % improvement in the execution time on average for applications having instruction accesses as a bottleneck, depending on the cache configuration. The improvement in execution time is as high as 23.5 % for some benchmarks. Categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles—Cache mem-ories; C.3 [Special-purpose and application-based sys-tems]: Real-time and embedded systems In CASES |
| File Format | |
| Language | English |
| Publisher Date | 2009-01-01 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
