NDLI: Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

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Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design

Content Provider	ACM Digital Library
Author	Datta, Suman Kulkarni, Jaydeep P. Saripalli, Vinay Narayanan, Vijaykrishnan
Abstract	Steep sub-threshold Interband Tunnel FETs (TFETs) are promising candidates for low supply voltage applications with higher switching performance than traditional CMOS. Unlike CMOS, TFETs exhibit uni-directional conduction due to their asymmetric source-drain architecture, and delayed output saturation characteristics. These unconventional characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show the utility of the Schmitt-Trigger feedback mechanism in improving the read/write noise margins, thus enabling ultra low-VCC operation for TFET SRAMs. We also propose a variation model for studying the impact of device-level variation on TFET SRAM cells. We show that the TFET ST SRAM cell has sufficient variation tolerance to operate at low-VCC, and is a very promising cell to achieve a VCC-min of 124mV. The TFET ST cell operating at its VCC-min provides a 1.2x reduction in dynamic energy and 13x reduction in leakage power compared to the best CMOS-based SRAM implementation operating at it's VCC-min, while giving better performance at the same time.
Starting Page	45
Ending Page	52
Page Count	8
File Format	PDF
ISBN	9781457709937
DOI	10.1109/NANOARCH.2011.5941482
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-06-08
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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