NDLI: Inexact computing for ultra low-power nanometer digital circuit design

Content Provider	ACM Digital Library
Author	Tiwari, Sandip
Abstract	We elaborated a new ultra low-power nanometer circuit design methodology by introducing statistical fluctuations in advanced technology nodes as noise sources causing computational errors. The modeling is performed on sub-50 nm technology node to create a statistical performance metric. The relationship between the probability of error and the circuit noise for a variety of different configurations and of circuit topologies is explored. Input-coupled noise has the dominant effect in terms of error and is analyzed through AC and high-frequency properties of the inverter transfer characteristics. Gate-level implementation of the probabilistic CMOS logic is validated with circuit simulations using a commercial 45-nm SOI CMOS process technology. Using a 32-bit adder where voltages can be scaled from MSB to LSB as an example, simulation results show the power of the technique. A calculation error of 10−6, a number quite appropriate for many computational tasks, occurs with a total power reduction of more than 40 %.
Starting Page	24
Ending Page	31
Page Count	8
File Format	PDF
ISBN	9781457709937
DOI	10.1109/NANOARCH.2011.5941479
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-06-08
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Inexact computing for ultra low-power nanometer digital circuit design