NDLI: Scaling application performance on a cache-coherent multiprocessor

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Maps: a compiler-managed memory system for raw machines

Dynamic vectorization: a mechanism for exploiting far-flung ILP in ordinary programs

PipeRench: a co/processor for streaming multimedia acceleration

Speculation techniques for improving load related instruction scheduling

Correlated load-address predictors

Selective value prediction

Tolerating late memory traps in ILP processors

Memory forwarding: enabling aggressive layout optimizations by guaranteeing the safety of data relocation

Decoupling local variable accesses in a wide-issue superscalar processor

Effective jump-pointer prefetching for linked data structures

Performance of image and video processing with general-purpose processors and media ISA extensions

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Is SC + ILP = RC?

Memory sharing predictor: the key to a speculative coherent DSM

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A scalable front-end architecture for fast instruction delivery

Area efficient architectures for information integrity in cache memories

Value prediction in VLIW machines

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Using network interface support to avoid asynchronous protocol processing in shared virtual memory systems

Multicast snooping: a new coherence method using a multicast address network

Scaling application performance on a cache-coherent multiprocessor

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Scaling application performance on a cache-coherent multiprocessor

Content Provider	ACM Digital Library
Author	Jiang, Dongming Singh, Jaswinder Pal
Abstract	Hardware-coherent, distributed shared address space systems are increasingly successful at moderate scale. However, it is unclear whether, or with how much difficulty, the performance of a load-store shared address space programming model scales to large processor counts on real applications. We examine this question using an aggressive case-study machine, the SGI Origin2000, up to 128 processors. We show for the first time that scalable performance can indeed be achieved in this programming model on a wide range of applications, including challenging kernels like FFT. However, this does not come easily, even for applications considered to be already highly optimized, and is very often not simply a matter of increasing problem size. Rather, substantial further application restructuring is often needed, which is usually quite algorithmic in nature. We examine how the restructurings compare with those needed for performance portability to shared virtual memory on clusters, and we comment on common programming guidelines for performance portability and scalability as well as on how the programming difficulty compares with that of explicit message passing. We also examine where applications spend their time on this large machine, the impact of special hardware features that the machine provides, and the impact of mapping to the network topology.
Starting Page	305
Ending Page	316
Page Count	12
File Format	PDF
ISBN	0769501702
DOI	10.1145/300979.301005
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1999-05-02
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scaling application performance on a cache-coherent multiprocessor

Software Caching on Cache-Coherent Multiprocessors (1992)

A Locally Cache-Coherent Multiprocessor Architecture

Scaling Application Performance on a Cache-coherent Multiprocessors (1999)

Performance evaluation of a commercial cache-coherent shared memory multiprocessor

The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors (1994)

FCache: a system for cache coherent processing on FPGAs

The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors (1994)

Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors (1998)

Scaling application performance on a cache-coherent multiprocessor

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Scaling application performance on a cache-coherent multiprocessor

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