NDLI: Exploiting pipelining to relax register-file port constraints of instruction-set extensions

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Exploiting pipelining to relax register-file port constraints of instruction-set extensions

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Exploiting pipelining to relax register-file port constraints of instruction-set extensions

Content Provider	ACM Digital Library
Author	Ienne, Paolo Pozzi, Laura
Abstract	Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). While these processors have become available, the state of the art on automatic ISE identification is improving; many algorithms are being proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the microarchitecture---some processors indeed only allow two read and one write ports---and, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. This paper proposes a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way for two reasons: (1) it exploits and brings forward the progress in ISE identification under constraint [1, 16, 4, 19] and (2) it combines register file access serialisation with pipelining in order to obtain the best global solution. This paper proposes an algorithm for scheduling graphs---corresponding to ISEs---under input/output constraint; experiments show that by using the proposed method applications can be sped-up tangibly: speedup for low I/O constraints is 32% better on average, and 65% better at best, than that obtained by state of the art techniques.
Starting Page	2
Ending Page	10
Page Count	9
File Format	PDF
ISBN	159593149X
DOI	10.1145/1086297.1086300
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-09-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Constrained scheduling Embedded customised architectures Input/output Multi-cycle register access Automatic instruction-set extension
Content Type	Text
Resource Type	Article

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