NDLI: Proceedings of the 24th edition of the great lakes symposium on VLSI (GLSVLSI '14)

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VLSI systems for neurocomputing and health informatics

Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis

Horizontal benchmark extension for improved assessment of physical CAD research

3D-SWIFT: a high-performance 3D-stacked wide IO DRAM

A performance enhancing hybrid locally mesh globally star NoC topology

Adaptive compressive sensing for low power wireless sensors

Squash: a scalable quantum mapper considering ancilla sharing

Create, then innovate

Smart nodes of internet of things (IoT): a hardware perspective view & implementation

WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-leveling

A hybrid framework for application allocation and scheduling in multicore systems with energy harvesting

A new DRAM architecture and its control method for the system power consumption

MB-FICA: multi-bit fault injection and coverage analysis

Simscape design flow for memristor based programmable oscillators

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip

EDA for extreme scale systems: design abstractions, metrics, and benchmarks

Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures

Generation of reduced analog circuit models using transient simulation traces

Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Optically reconfigurable gate array with an angle-multiplexed holographic memory

System-level reliability exploration framework for heterogeneous MPSoC

OCV-aware top-level clock tree optimization

Minimum implant area-aware gate sizing and placement

VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract

Regulator-gating: adaptive management of on-chip voltage regulators

Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory

Reliability-aware cross-point resistive memory design

Neural network-based accelerators for transcendental function approximation

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

Securely outsourcing power grid simulation on cloud

A generic implementation of a quantified predictor on FPGAs

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator

Forward-scaling, serially equivalent parallelism for FPGA placement

A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers

Level shifter planning for timing constrained multi-voltage SoC floorplanning

Variability-aware design of double gate FinFET-based current mirrors

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness

Modeling of the charging behavior of li-ion batteries based on manufacturer's data

A multi-stage leakage aware resource management technique for reconfigurable architectures

Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control

Logic block and design methodology for via-configurable structured ASIC using dual supply voltages

A study on the use of parallel wiring techniques for sub-20nm designs

Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems

Efficient parallel beamforming for 3D ultrasound imaging

New 4T-based DRAM cell designs

A novel parallel adaptation of an implicit path delay grading method

An automated design approach to map applications on CGRAs

A dual-rail LUT for reconfigurable logic using null convention logic

Thermal-aware phase-based tuning of embedded systems

A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction

A qualitative simulation approach for verifying PLL locking property

Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs

A comparison of FinFET based FPGA LUT designs

A feasibility study on robust programmable delay element design based on neuron-MOS mechanism

High level energy modeling of controller logic in data caches

A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters

A new methodology for reduced cost of resilience

A task-oriented vision system

He-P2012: architectural heterogeneity exploration on a scalable many-core platform

WeDBless: weighted deflection bufferless router for mesh NoCs

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield

Trade-off between energy and quality of service through dynamic operand truncation and fusion

Transient analysis of gate inside junctionless transistor (GI-JLT)

A novel low-power and in-place split-radix FFT processor

Built-in generation of functional broadside tests considering primary input constraints

H.264 8x8 inverse transform architecture optimization

TSV power supply array electromigration lifetime analysis in 3D ICS

Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas

A current-mode CMOS/memristor hybrid implementation of an extreme learning machine

Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories

Performance modeling of virtualized custom logic computations

A design flow for physical synthesis of digital cells with ASTRAN

Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]

A semi-formal approach for analog circuits behavioral properties verification

An area efficient low power high speed S-Box implementation using power-gated PLA

FPGA based implementation of a genetic algorithm for ARMA model parameters identification

Highly adaptive and congestion-aware routing for 3D NoCs

Proceedings of the 24th edition of the great lakes symposium on VLSI (GLSVLSI '14)

Content Provider	ACM Digital Library
Editor	Chen, Xi Cavallaro, Joseph Macii, Alberto Margala, Martin Sun, Zhenyu Niu, Dimin Homayoun, Houman Gordon-Ross, Ann Chen, Ke Papandreou, Nikolaos Lingasubramanian, Karthikeyan Jones, Alex K. Cavallaro, Joseph R. Luo, Yan Mohanty, Saraju Li, Hai Helen Ghosal, Prasun Kose, Selcuk Kumar, Akash Zhang, Tong Lin, Rung-Bin
Copyright Year	2014
Abstract	Welcome to the 24th edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2014 held in Houston, Texas. GLSVLSI is a premier venue for the dissemination of manuscripts of the highest quality in all areas related to VLSI, devices and system level design. The venue of this year's GLSVLSI is Houston, which not only has a "Lake Houston" nearby but also is located right next to "Great Gulf of Mexico". You will enjoy the beautiful scenery surrounding Houston as well as the program over the two and a half days of this year's GLSVLSI activity. As for the technical meeting, GLSVLSI 2014 was a resounding success: 179 papers were submitted, including authors from 30 different countries, of which 49 papers were accepted for oral presentation at the symposium (a 27.4% acceptance rate). With poster papers, a total of 76 papers will be presented at the symposium and published in the conference proceedings. The final technical program consists of 29 full presentations and 20 short presentations in 15 oral sessions and 27 posters in two poster sessions. Of these papers in the program, 55.8% are from North America, 18.2% from Asia, 20.8% from Europe, and 5.2% from South America/Australia. GLSVLSI 2014 starts on Wednesday, May 21st, in the morning with an invited keynote talk "VLSI Systems for Neurocomputing and Health Informatics" by Keshab Parhi, University of Minnesota, followed by technical sessions on Reliability, CAD, Energy Efficient Systems, and System Design Methodologies, and an inspiring and entertaining dinner keynote talk "Create, then Innovate" by Gene Frantz. Then, the technical program continues on Thursday, May 22nd with the second invited keynote talk "Smart Nodes of Internet of Things (IoT): A Hardware Perspective View & Implementation" by Edgar Sanchez-Sinencio, Texas A&M University, followed by technical sessions which present the latest industrial and academic research covering topics such as Fault-tolerance, Application-specific Circuits and Systems, Reconfigurable Elements, and System-level Optimization. The conference will end by the noon of Friday, May 23rd after the third keynote talk "EDA for Extreme Scale Systems" by Alex Jones, University of Pittsburgh, and sessions on topics of Reconfigurable Systems, Analog Design, Low Power Design, and Emerging Technologies during the morning. Overall, there are 15 regular sessions in the technical program including a session where the "best paper award" candidates will have the opportunity to present their outstanding work.
ISBN	9781450328166
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-05-20
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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